The Ripple Counter
Counters are everywhere: timers, clock dividers, address generators, the program counter in a processor. This section builds them, starting with the cheapest one possible and finding out why cheapest is not best.
The chain
In a binary count, bit 0 toggles every cycle, bit 1 every second cycle, bit 2 every fourth, and bit $n$ every $2^n$ cycles. A T flip-flop with T tied to 1 toggles on every clock it receives, so if the output of one clocks the next, each stage divides by two and produces the next bit of the count (Figure 1). Four flip-flops, no gates. This is the ripple counter, also called an asynchronous counter, and it is the T flip-flop chain from section 3.1.
With flip-flops that toggle on the falling edge of their clock input, Q1 toggles when Q0 falls, Q2 when Q1 falls, and so on, and the outputs count 0 to 15 and wrap.
The ripple delay
Each flip-flop takes a clock-to-Q delay $t_{cq}$ to respond, and each is clocked by the previous one. So Q0 settles $t_{cq}$ after the clock edge, Q1 settles $2t_{cq}$ after it, Q2 at $3t_{cq}$ and Q3 at $4t_{cq}$. For $N$ bits the top bit settles $N t_{cq}$ after the edge, and until then the outputs are not a valid count (Figure 2).
Take the step from 7 to 8. All four bits should change together. In the ripple counter they change one after another:
| Time | Q3 Q2 Q1 Q0 | Reads as |
|---|---|---|
| before the edge | 0 1 1 1 | 7 |
| $t_{cq}$ | 0 1 1 0 | 6 |
| $2t_{cq}$ | 0 1 0 0 | 4 |
| $3t_{cq}$ | 0 0 0 0 | 0 |
| $4t_{cq}$ | 1 0 0 0 | 8 |
On the way from 7 to 8 the counter reads 6, 4 and 0. Those are real values on real wires. Anything that decodes the count, a 4-to-16 decoder or a comparator looking for zero, will fire briefly on each of them at every carry. Never feed a ripple counter’s outputs into logic that needs all the bits valid at once.
Speed
For the count to be valid before the next edge, the clock period has to exceed the whole ripple plus whatever setup time follows:
$$T_{clk} > N, t_{cq} + t_{su}$$
With a 1 ns flip-flop, a 4-bit ripple counter is limited to about 250 MHz, an 8-bit one to 125 MHz, and a 32-bit one to about 31 MHz. The maximum frequency falls as $1/N$. A synchronous counter, in the next article, is nearly independent of width.
Where it is fine
A ripple counter is still the right choice in some places. For a clock divider, where the output only goes to another clock input and nobody decodes the intermediate bits, the ripple delay does not matter; each output is a clean square wave, just delayed. At low speed, in a timer or a blinking LED, the absence of any logic is a saving. And it uses less power than a synchronous counter, because each stage toggles at half the rate of the one before it and there is no enable logic switching every cycle. A real-time clock chip that divides a 32.768 kHz crystal down to one second is exactly this circuit.
Practice Exercise
Problem 1. A 4-bit ripple counter with 2 ns flip-flops drives a 4-to-16 decoder. What is the worst-case settling time, and which decoder outputs pulse falsely on the 7 to 8 transition?
Solution
$4 \times 2 = 8$ ns. Outputs 6, 4 and 0 each pulse for about 2 ns before output 8 settles.
Problem 2. Build a 1 Hz signal from a 32.768 kHz crystal. How many stages, and is a ripple counter appropriate?
Solution
$32768 = 2^{15}$, so fifteen stages; the fifteenth output toggles once a second. A ripple counter is ideal here: the clock period is 30 µs, the ripple is tens of nanoseconds, and the output drives another counter, not decode logic.
Problem 3. A 3-bit ripple counter starts at 5 and receives four clocks. Where does it end?
Solution
5, 6, 7, 0, 1. It ends at 1, which is $(5 + 4) \bmod 8$.
The fix for the ripple problem is to clock every flip-flop from the same clock and use logic to decide which bits toggle. That is the synchronous counter of the next article.