Courses
Learn Digital Design, Systematically
The articles on this site cover individual topics. The courses here connect those topics into a deliberate learning path — each one taking you from first principles to real, working hardware.
Every course is built around three ideas:
- Foundations before frameworks. You will understand why things work before you memorize how to use them.
- Hardware thinking, not software thinking. Digital design has its own mental model. These courses build it explicitly.
- Verification as a first-class skill. Writing RTL that simulates correctly is half the job. Proving it is the other half.
Available Courses
Digital Design & Verilog: From Basics to Hero
A complete ground-up course covering digital logic foundations, RTL design in Verilog, testbench writing, advanced design patterns, and SystemVerilog — ending with five capstone projects. Suitable for complete beginners and practising engineers filling in gaps.
10 modules · 60+ posts · 5 capstone projects
Topics covered: Number systems · Boolean algebra · Logic gates · Karnaugh maps · Combinational circuits · Sequential circuits · FSMs · Verilog RTL · Testbenches · Pipelines · FIFOs · Clock domain crossing · SystemVerilog · Assertions
RTL to GDSII: ASIC Physical Design with OpenLane & SkyWater
A hands-on physical design course covering the complete flow from a synthesized netlist to a signed-off GDSII — floorplanning, placement, clock tree synthesis, routing, timing closure, and physical verification — using the open-source OpenLane flow and the SkyWater SKY130 PDK. Builds directly on the RTL fluency from the Verilog course above.
10 modules · 45+ posts · 5 capstone projects
Topics covered: OpenLane & the open-source EDA stack · SKY130 PDK · Synthesis · Floorplanning · Placement · Clock tree synthesis · Routing · Static timing analysis · DRC & LVS · Antenna rules · GDSII & tapeout
More courses are in development. Follow the YouTube channel for updates.