Finding and Fixing an Antenna Violation on the UART

In the last two articles we covered the antenna mechanism and the two ways to fix it. In this article we run the check on the routed UART. Antenna checking runs after detailed routing, because it needs the final geometry of every layer, and it belongs to the same signoff gate as DRC and LVS: the design does not move on until it is clean.

Running the antenna check

OpenROAD has a built-in antenna checker that works directly on the routed database. For every net it works out, layer by layer, how much metal is connected to each gate at that layer’s etch step, divides by the gate area and compares with the limits from the technology LEF, which is the calculation from the first article of this section.

openroad
% read_lef $PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef
% read_lef $PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef
% read_def runs/uart_full/results/routing/uart_top.def
% check_antennas -verbose

OpenLane runs this check at the end of routing and puts the result in its reports directory with the DRC and LVS results. It also runs repair_antennas after global routing, so most at-risk nets already have diodes. The occasional violation still survives, because detailed routing changes the geometry slightly after the repair has made its decisions. That is what happened on our UART.

Reading the report

The summary and the verbose detail for the failing net look something like this (the exact layout of the output varies between OpenROAD versions):

Net: baud_div_out
  Pin: tx_clkgate/GATE (sky130_fd_sc_hd__dlclkp_1)
    Layer: met2
      Partial area ratio:  1647.00 (Required:  400.00) VIOLATED
      Gate area: 0.090 um^2   Metal side area: 148.2 um^2

[INFO ANT-0002] Found 1 net violations.
[INFO ANT-0001] Found 1 pin violations.

One violation, on baud_div_out, the same net we broke and repaired in the LVS lab. Its met2 partial ratio is 1647 against a limit of 400, more than four times over. The gate it threatens is the GATE pin of the transmit clock gate, a dlclkp_1, which is a compact cell with small input transistors and so a small gate area.

Why this net

It is worth understanding why this net failed before fixing it. Highlight it in the OpenROAD GUI, or look at its routing in the DEF, and you see a single met2 run of about 200 µm, joined to the clock gate’s input through a via at one end, while the connection to the driving flop’s output comes in later through met3. While met2 is being etched, all of that met2 hangs on the clock gate’s input and on nothing else. Long run, one layer, small gate at the end, with the diffusion connection coming later: the risk profile from the first article.

Applying the fix

The path from baud_div_out to the clock gate has more than a nanosecond of setup slack at every corner, so a diode’s fraction of a femtofarad makes no timing difference here, and diode insertion is what the tools do reliably. The fix is to repeat antenna repair from global routing with some extra margin, so the repair also treats nets that are only just under the limit, and then route again:

% global_route -congestion_iterations 50
% repair_antennas sky130_fd_sc_hd__diode_2 -iterations 3 -ratio_margin 20
% detailed_placement
% check_placement
% detailed_route
% check_antennas -verbose

repair_antennas inserts diodes next to the gates of nets that violate on the global routes. -ratio_margin 20 makes it treat the limits as 20% tighter than they are, so nets that pass with little room also get a diode and are less likely to be pushed over the limit by the detailed router. detailed_placement makes room for the new diode cells on legal sites, and the detailed route then connects them. In OpenLane you get the same effect by raising the antenna repair margin setting of the global routing step and re-running the flow from there.

After the repair, the log shows one diode inserted on baud_div_out, placed right beside tx_clkgate, and the checker reports:

[INFO ANT-0002] Found 0 net violations.
[INFO ANT-0001] Found 0 pin violations.

The net’s met2 metal has not changed. What changed is that the net now has a diffusion, the diode, connected at met1 right next to the gate, so during the met2 etch the charge has somewhere safe to go. That is also why the limit reported for this net rises once a diode is attached: the rules allow more metal when diffusion is connected.

The cause of the violation deserves one more thought. A jumper, bringing the long met2 run onto the gate only through met3, would also have fixed it, with no new cell. If this net had been on a tight path, that is the fix I would have asked for. Here the diode is simpler and costs nothing that matters.

Checking that nothing else moved

Any change to the layout sends you back through the earlier checks. Adding a cell and re-routing means:

• DRC again, since the diode and its new connection are new geometry.
• LVS again, against a netlist written after the repair, so both sides include the new diode. Comparing against the old netlist would report an extra device, which is the situation in the Module 10 debugging project.
• A timing check on the affected net, as part of the final signoff STA.

In our case all three come back clean, which is what you expect from a single diode on a net with plenty of slack. It is still worth running them, because “it should be fine” is not a signoff result.

Practice Exercise

Suppose that after the repair, a different net reports a met2 partial ratio of 394 against a limit of 400: technically passing, with very little room. Would you accept it, and what would you check before deciding?

DRC, LVS and antenna checks together tell us the layout is buildable, correct and will not damage itself during fabrication. None of them asks whether every cell actually gets enough supply voltage once current flows. That is the subject of the next section.