Verilog, VHDL and SystemVerilog

There are three hardware description languages in use, and people argue about them the way they argue about editors. The argument matters less than it seems. All three describe the same flip-flops and gates, and once you can think in one, the others are a few weeks of syntax. This article says what each is, shows the same circuit in all three, and explains the choice made for this course.

Verilog, IEEE 1364

Created at Gateway in 1984 as a simulator input language and standardised in 1995, as the previous articles described. Its syntax descends from C: begin and end in place of braces, if, case, and a general terseness that C programmers find comfortable. Verilog-2001 is the version that matters, and 2005 was the last standalone revision. You will find it at American and Asian semiconductor companies, in open-source cores, and in the legacy RTL of nearly everyone who has shipped a chip.

VHDL, IEEE 1076

Commissioned by the US Department of Defense in the early 1980s as part of the VHSIC programme, with a lineage from Ada: strongly typed, verbose, designed for maintainability and formal review. Revisions in 1993, 2008 and 2019. The verbosity that makes it slow for prototyping makes it good for safety-critical work, because every type is explicit and the compiler catches mismatches that Verilog would quietly coerce. You will find it in Europe, in defence and aerospace, and wherever DO-254 or ISO 26262 certification is involved.

SystemVerilog, IEEE 1800

A superset of Verilog-2005, standardised from 2005 onwards, with two largely separate additions. For RTL: the logic type in place of the wire and reg distinction, always_ff, always_comb and always_latch to declare intent, interfaces, structs, enums and typedefs. For verification: classes, constrained random stimulus, functional coverage, assertions, and the machinery that the UVM methodology is built on. Synthesis tools consume the first half; verification engineers write testbenches in the second. It is the standard for new designs today.

One flip-flop, three ways

A D flip-flop with synchronous active-low reset.

Verilog-2001:

`timescale 1ns / 1ps
`default_nettype none

module dff_v2001 (
    input  wire clk,
    input  wire rst_n,  // synchronous, active low
    input  wire d,
    output reg  q
);

    always @(posedge clk) begin
        if (!rst_n)
            q <= 1'b0;
        else
            q <= d;
    end

endmodule

VHDL-2008:

library ieee;
use ieee.std_logic_1164.all;

entity dff_vhdl is
    port (
        clk   : in  std_logic;
        rst_n : in  std_logic;  -- synchronous, active low
        d     : in  std_logic;
        q     : out std_logic
    );
end entity dff_vhdl;

architecture rtl of dff_vhdl is
begin
    process(clk) is
    begin
        if rising_edge(clk) then
            if rst_n = '0' then
                q <= '0';
            else
                q <= d;
            end if;
        end if;
    end process;
end architecture rtl;

SystemVerilog:

`timescale 1ns / 1ps
`default_nettype none

module dff_sv (
    input  logic clk,
    input  logic rst_n,
    input  logic d,
    output logic q
);

    always_ff @(posedge clk) begin
        if (!rst_n)
            q <= 1'b0;
        else
            q <= d;
    end

endmodule

The VHDL has library, entity, architecture and process around the same three lines of logic. The SystemVerilog is the Verilog with logic for wire and reg and always_ff for always. That last one is not decoration: a synthesiser will refuse an always_ff block that does not produce flip-flops, which catches a class of mistakes that plain always lets through.

Why Verilog-2001 here

Every tool accepts it, including all the free ones, and this course leans on Icarus Verilog and Yosys, whose SystemVerilog support is partial. Everything you learn transfers one for one, since the RTL subset of SystemVerilog is Verilog with refinements. Most of the RTL you will read and modify in your career is Verilog-2001. And for teaching, wire and reg are more explicit than logic: understanding that reg does not mean a register, and that wire is a continuously driven net, builds the right picture, and logic hides that lesson while being the better production choice.

Module 9 makes the move to SystemVerilog RTL, by which point each addition will look like the answer to a problem you have already met. The verification side of SystemVerilog is its own discipline and gets its own module.

If you end up at a European company or a defence contractor you will meet VHDL, and it will take about two weeks. The concepts are the same, the synthesiser behaves the same, and the difference is an accent rather than a language.

Practice Exercise

Write a 4-bit synchronous counter with active-low reset in Verilog-2001, then in SystemVerilog with always_ff and logic, and list the differences.

`timescale 1ns / 1ps
`default_nettype none

module counter_v2001 (
    input  wire       clk,
    input  wire       rst_n,
    output reg  [3:0] count
);
    always @(posedge clk) begin
        if (!rst_n)
            count <= 4'd0;
        else
            count <= count + 4'd1;
    end
endmodule

`timescale 1ns / 1ps
`default_nettype none

module counter_sv (
    input  logic       clk,
    input  logic       rst_n,
    output logic [3:0] count
);
    always_ff @(posedge clk) begin
        if (!rst_n)
            count <= 4'd0;
        else
            count <= count + 4'd1;
    end
endmodule

Before writing any RTL there is one more thing to settle, and it is the hardest part of the whole language: Verilog looks like C, and thinking like a C programmer produces broken hardware. The next article is about that.