Pin Order and Side Assignment

Section 3.2 delivered power. Section 3.3 is about the signal pins on the boundary.

counter8 has eleven pins: clk, rst_n, en, and the 8-bit count output. By default OpenLane spaces all eleven evenly around the perimeter without asking, equidistant placement, no config needed. For a design this small that may work fine. It is worth understanding why it might not, because the same automatic placement on a bigger, busier design quietly hands you a routing problem you will not see until Module 6.

Why pin location is not cosmetic

A wire from a pin to the logic that uses it has to route from the boundary, through the margin, into the core, to wherever that logic sits. The farther the pin from the logic, the longer the route, the more tracks it uses on the way, and the more it competes with everything else routing through the same corridor. Two strategies exist:

Tool-assigned, equidistant: OpenLane spaces every pin evenly around the perimeter in port declaration order, with no regard for where each pin’s logic ends up. Fast, zero effort, fine for small or non-critical designs.
Explicit fixed order: you tell OpenLane which side, and the order within the side, each pin goes on, through a pin order file (the third article of this section). A little thought up front for shorter, less congested routes to the pins that matter.

On designs with a known package or board pinout, a pin that must land at a specific spot because a PCB trace or bond wire is already committed, explicit order is not optional; it is a hard requirement the floorplan has to satisfy regardless of what is best for internal routing.

Assigning counter8’s ports by hand

The ports group cleanly:

Port	Direction	Width	Role
`clk`	input	1	Clock, feeds every flip-flop
`rst_n`	input	1	Active-low reset, feeds every flip-flop
`en`	input	1	Count enable, feeds the increment logic
`count[7:0]`	output	8	Counter value, driven by the flip-flop bank

The grouping principle: put signals that share a destination on the same side, and keep unrelated signal classes apart so their routes do not cross unnecessarily.

counter8 with clk, rst_n and en on the west edge and count[7:0] on the east edge — Figure 1: Control on the west, the count bus on the east

clk, rst_n and en, the three control signals that fan out to the flip-flop bank and its enable logic, go on the west side together. The count output, one cohesive bus driven straight off the flip-flops, goes on the east in bit order, so the bus stays a clean parallel group. North and south are left empty. counter8 does not have enough distinct pin roles to need all four sides, and there is no rule that it must.

Do not split a bus across two sides “to balance the pin count”. It looks tidier on paper, but it forces the router to reconverge the bus’s bits once they are inside the core, adding wire length and congestion for no benefit. Keep buses together.

Practice Exercise

A design has ports clk, rst_n, spi_mosi, spi_miso, spi_sclk, spi_cs_n, and an unrelated 4-bit status[3:0] output. Propose a side assignment.

Solution

A reasonable assignment: clk and rst_n on one side (west, by convention for global control) since they fan out to nearly every flop; the four spi_* signals together on a second side (south, say), since they are one interface that will connect to one SPI controller block; and status[3:0] on a third side (east), kept together as a bus. The judgement call is recognising that spi_mosi, spi_miso, spi_sclk and spi_cs_n are one functional group even though their directions differ. Direction does not determine grouping; shared destination logic does.

Side assignment answers which edge. In the next article we look at a question that can override everything just decided: what if the die’s minimum size is set not by the core at all, but by how many pads have to fit around it?