Configuring a Power Grid in OpenLane

Everything in the last two articles, a ring, a few straps, reasoning about which cells sit close to one, has a direct config-field equivalent in OpenLane. There is no new model here, only the vocabulary OpenLane uses for the one you already have.

The knobs

PDN generation is controlled by a family of FP_PDN_* fields in config.json. The ones that map onto the sketch:

Field	Controls
`FP_PDN_CORE_RING`	Whether a ring is generated around the core at all
`FP_PDN_VWIDTH` / `FP_PDN_HWIDTH`	Width of vertical and horizontal straps (and ring segments)
`FP_PDN_VPITCH` / `FP_PDN_HPITCH`	Centre-to-centre spacing between vertical and horizontal straps
`FP_PDN_VOFFSET` / `FP_PDN_HOFFSET`	Where the first strap in each direction starts, relative to the core edge
`FP_PDN_VERTICAL_LAYER` / `FP_PDN_HORIZONTAL_LAYER`	Which metal layers carry the vertical and horizontal grid (typically the thick upper layers)

For the 40 by 40 µm counter8 core, a config section built from the sketch, three straps each way spaced about a third of the core apart:

{
  "FP_PDN_CORE_RING": 1,
  "FP_PDN_VWIDTH": 1.6,
  "FP_PDN_HWIDTH": 1.6,
  "FP_PDN_VPITCH": 13.3,
  "FP_PDN_HPITCH": 13.3,
  "FP_PDN_VOFFSET": 6.5,
  "FP_PDN_HOFFSET": 6.5,
  "FP_PDN_VERTICAL_LAYER": "met4",
  "FP_PDN_HORIZONTAL_LAYER": "met5"
}

A 13.3 µm pitch across a 40 µm core places straps at roughly 6.5, 19.8 and 33.1 µm from the core edge, three interior crossings each way. These numbers illustrate the pitch and offset relationship; a PDK-validated run would settle its own.

Strap width and pitch have to respect the PDK’s minimum width and spacing for the chosen layer. OpenLane rejects a PDN configuration that violates SKY130’s rules for met4 and met5 rather than generating an illegal grid. If you hit that error, the fix is almost always to widen the pitch or narrow the strap, not to override the check.

Running it

In interactive mode, PDN generation happens inside the floorplan step, after the core and die geometry is set:

% prep -design counter8
% run_floorplan
[INFO]: Generating floorplan...
[INFO]: Core area set to 5.00 5.00 45.00 45.00 (die 0.00 0.00 50.00 50.00)
[INFO]: Generating power distribution network...
[INFO]:   Core ring: met4/met5, width 1.60, offset 2.00
[INFO]:   Vertical straps (met4): 3 straps, pitch 13.30, width 1.60
[INFO]:   Horizontal straps (met5): 3 straps, pitch 13.30, width 1.60
[INFO]: Writing floorplan DEF to runs/<tag>/results/floorplan/counter8.floorplan.def

The log is doing what the first article’s sketch did, with real geometry and real layer names. The DEF now contains SPECIALNETS entries for VPWR and VGND, the ring and strap polygons on met4 and met5 at the coordinates OpenLane computed from your pitch and offset. You will open this file in Magic or KLayout at the end of the module and see those shapes for the first time.

Every PDN knob is a dial on the IR-drop trade from the previous article. A tighter pitch means a shorter average distance from any cell to a strap and lower worst-case drop, at the cost of routing resources consumed by the grid instead of by signal nets. There is no free lunch, only a choice of where to spend it.

From the config above, work out roughly how far the core’s centre (20, 20 in core coordinates) sits from the nearest strap crossing. With straps at about 6.5, 19.8 and 33.1 µm each way, the nearest crossing is at (19.8, 19.8), within about 1 µm of centre. That is a deliberately favourable outcome for a small design; on a larger core with the same pitch, more of the interior would sit farther from a crossing.

Practice Exercise

You inherit a config with FP_PDN_VPITCH set to 60 for a 40 µm wide core. What does that imply about how many interior vertical straps are generated, and is it reasonable for this core?

Solution

A 60 µm pitch is wider than the whole 40 µm core, so at most one vertical strap (plus the ring) fits, effectively no interior strapping. That is a poor setting: by the previous article’s reasoning, most of the interior would be far from any strap, spreading IR drop risk across nearly the whole core instead of the small pockets a properly pitched grid leaves. Shrink FP_PDN_VPITCH to something meaningfully smaller than the core dimension, as the worked example did with 13.3 µm on a 40 µm core.

The power grid is built. In the next section we turn to a different floorplan decision: where every I/O pin on the die boundary lands, starting with pin order and side assignment.