Module 10: Capstone Projects
Nine modules, and no theory left to introduce. Everything from here is application: five complete, realistic RTL systems, each built the way real engineering happens, starting from a specification rather than a blank slate, and ending in a verified self-checking simulation rather than a design you hope is correct.
There is nothing new to learn in this module, and that is the point. If you find yourself reaching for something you do not remember, it is almost certainly a callback to a specific earlier article, and every project below points you back to the right one rather than re-explaining it. This module is where you find out what nine modules of foundations add up to.
The five projects
The projects are independent of each other. You can do them in any order, or only the ones relevant to your own goals, but they are presented in an order that roughly tracks increasing protocol complexity:
| Project | What you build | Draws most on |
|---|---|---|
| 1, RISC Processor Core | A working, if minimal, instruction-fetching, decoding, executing processor | Module 2 (ALU), Module 3 (FSMs, registers), Module 5 (RTL FSMs) |
| 2, UART Controller | A serial transmitter and receiver with configurable baud rate | Module 3 (shift registers, counters), Module 6 (testbenches) |
| 3, SPI Master | A configurable master supporting all four SPI clock modes | Module 5 (FSMs), Module 7 (parameterization) |
| 4, SRAM Controller | Correct read/write timing against a parameterized memory model | Module 7 (memory models), Module 8 (timing discipline) |
| 5, AXI4-Lite Slave | A standardized bus protocol slave with a register file | Module 9 (interfaces, assertions), Module 7 (handshakes) |
What complete means here
Every project follows the same four stages:
- Specification: understanding the protocol or architecture well enough to write a precise behavioural contract before any RTL.
- Datapath: the arithmetic, storage and data-movement structures, built from the primitives in Modules 2, 3 and 7.
- Control: the FSM or FSMs sequencing the datapath, in the Module 5 coding styles with the safe-encoding discipline from Modules 5 and 9.
- Verification: a self-checking testbench proving the implementation meets the specification from step 1, using the Module 6 structure and, where it adds value, the randomization and assertions from Module 9.
A project that skips step 1 and jumps to RTL tends to produce a design that seems to work against whatever tests the author thought of, which is exactly the gap Module 6’s self-checking philosophy and Module 9’s constrained-random testing exist to close. Take the specification stage seriously. It is not preamble; it is the definition of what correct means for everything after it.
A note on scope
None of the five projects is a production, tape-out quality implementation. A real UART, SPI controller or AXI4-Lite slave in a shipping chip carries more configuration options, error handling and edge cases than a course project can include. What each project does deliver is a functionally complete, verified core implementation of the real protocol or architecture, built with the discipline a production version would need (parameterization, timing awareness, self-checking verification), scaled to what is achievable in a project without being simplified in a way that would teach you something wrong.
Every project starts the same way, with a specification precise enough to know what you are building before you build it. Project 1 starts there, designing a minimal but complete instruction set for an 8-bit processor before a single always block is written. Start with Project 1, the 8-bit RISC processor core.