Project 5, Part 1: AXI4-Lite, Five Independent Handshakes
Project 4 was about respecting an external timing contract. Project 5 is about respecting an external protocol contract, and this protocol is different in kind from Projects 2 and 3. UART and SPI are each one protocol moving one stream of bits in a fixed sequence. AXI4-Lite is five separate, independently handshaked channels, each with its own ready/valid pair, running concurrently. It is the standardized descendant of the ready/valid backpressure idea from the Section 7.3 stall article, and it is the interconnect used across essentially the whole modern SoC industry.
The five channels
| Channel | Direction | Carries |
|---|---|---|
| Write Address (AW) | master to slave | The address of a pending write |
| Write Data (W) | master to slave | The data being written |
| Write Response (B) | slave to master | Confirmation the write completed, and whether it succeeded |
| Read Address (AR) | master to slave | The address of a pending read |
| Read Data (R) | slave to master | The data read back, plus a response status |
Five channels, each carrying different information, each with its own handshake. This project builds the slave side, the usual project for a peripheral register interface. A master role is what a CPU or DMA engine plays; a slave is the peripheral being controlled.
Every channel uses the same ready/valid handshake
This is the one idea every channel shares, and it is the Section 7.3 backpressure pattern applied five times. Figure 1 shows one channel.
A transfer on a channel completes on the clock edge where both VALID (driven by the sender) and READY (driven by the receiver) are high. Neither has to come first. Either side asserts its own signal whenever it is ready and waits for the other. This is deliberately more flexible than the request/acknowledge sequencing in Section 7.5, where req had to rise before ack could respond. Here VALID and READY are independent, and a receiver may assert READY before it has seen any VALID. One rule does apply to the sender: once VALID is asserted it must stay asserted, with the data unchanged, until the transfer completes.
Why write address and write data are separate channels
Why does AXI4-Lite split one logical operation, “write this data to this address”, across two channels with independent handshakes, rather than bundling them as the Section 7.1 ram_dp model did?
Throughput and flexibility. Because AW and W are independent, a master can send the address slightly ahead of, behind, or alongside the data, whichever suits its own pipeline (recall Section 7.3), without either channel stalling the other unnecessarily. A slave, in turn, has to accept the two in either order and only perform the write once it has both.
The ordering rule
One rule ties the channels together and prevents a deadlock: the write response on the B channel for a given transaction must not be issued until both the AW and W transfers have completed. This is a specification-mandated ordering constraint, and it is exactly the kind of multi-cycle, cross-channel property the Module 9 concurrent assertions are built to check continuously, rather than hoping a hand-written testbench remembers to verify it in every interleaving.
Full AXI adds bursts, multiple outstanding transactions and out-of-order responses. AXI4-Lite strips all of that away, keeping the five-channel ready/valid structure while restricting every transaction to a single beat, so that simple register interfaces like this project’s do not need the machinery high-performance masters and memory controllers do. Understanding AXI4-Lite is the practical foundation for reading full AXI.
Practice Exercise
A master asserts AWVALID on cycle 0 but the slave does not assert AWREADY until cycle 3. Separately, the master asserts WVALID on cycle 1 and the slave asserts WREADY on cycle 1. On which cycle does each channel’s transfer complete, and why can the write not be considered complete until the later of the two?
Solution
The AW transfer completes on cycle 3, the first cycle where both AWVALID (high since 0) and AWREADY (high from 3) are high. The W transfer completes on cycle 1. Although the data arrived and was accepted first, the write cannot be complete, and the B response cannot be issued, until the later of the two, cycle 3, because the slave only has a valid address to write the data to once AW has completed. That is the ordering rule: independent channel timing is allowed, but the write is complete only when every channel it depends on has completed.
AXI4-Lite is five channels, not one protocol, each with its own ready/valid handshake descended from Section 7.3 but generalised so that neither signal has to come first. Write address and data are decoupled so a master’s pipeline can present them in whatever order suits it, with the slave responsible for waiting on both before committing and responding. In the next article we build the register file and the handshake logic that implements this five-channel contract in RTL.