The Ripple-Carry Adder
In the previous article we built the full adder. In this one we chain $N$ of them into an $N$-bit adder. Think of a row of dominoes: each one falls only after the one before it, and if each takes 2 ns, a row of 64 takes 128 ns, not because any step is slow but because every step waits for the last. That is the ripple-carry adder. It is correct and simple, and for wide operands at high clock rates it is too slow. You need to see exactly why and exactly how slow before the faster adders make sense, so let us build one and do the arithmetic.
Building it
The full adder’s carry-out becomes the next full adder’s carry-in. Chain two and you have a 2-bit adder, chain $N$ and you have an $N$-bit adder:
- Place full adders FA0 to FA$(N-1)$ from least to most significant bit.
- Tie the carry-in of FA0 to 0 (or to an external carry-in).
- Connect the carry-out of FA$i$ to the carry-in of FA$(i+1)$.
- The sum bits $S_0 \ldots S_{N-1}$ are the result, and the carry-out of FA$(N-1)$ is the adder’s carry-out, which signals unsigned overflow.
Figure 1 shows the 4-bit version. The structure is so regular that it maps straight onto a loop in an HDL, which is one reason it has survived as both a teaching example and a practical choice for narrow adders.
Tracing 0110 + 0101
$A = 0110$ (6) and $B = 0101$ (5); we expect 1011 (11) with no carry out.
FA0: $A_0 = 0$, $B_0 = 1$, $C_0 = 0$. $S_0 = 0 \oplus 1 \oplus 0 = 1$. $C_1 = 0$.
FA1: $A_1 = 1$, $B_1 = 0$, $C_1 = 0$. $S_1 = 1$. $C_2 = 0$.
FA2: $A_2 = 1$, $B_2 = 1$, $C_2 = 0$. $S_2 = 0$. $C_3 = 1$.
FA3: $A_3 = 0$, $B_3 = 0$, $C_3 = 1$. $S_3 = 1$. $C_4 = 0$.
Result $1011$, carry out 0. Correct. Notice that FA1 could not settle until FA0 had produced $C_1$, FA2 waited on $C_2$, and FA3 waited on $C_3$. FA3 finished last, and how long it took was set entirely by the chain before it.
The critical path
For timing I use the direct AND-OR form of the carry from the last article, so that $C_{in}$ to $C_{out}$ through one full adder is two gate delays, and the final carry into a sum bit is one more XOR.
The worst-case path runs through the whole carry chain and then into the top sum bit:
- $C_0$ to $C_1$: 2 gate delays
- $C_1$ to $C_2$: 2
- and so on, $N$ stages: $2N$
- $C_{N-1}$ to $S_{N-1}$: 1 more XOR
Adding the initial gate delay to form the first carry from $A_0$ and $B_0$ gives roughly
$$t_{RCA}(N) \approx 2N + 2 \text{ gate delays}$$
| Width | Gate delays | Time at 100 ps per gate | Maximum clock |
|---|---|---|---|
| 4 | 10 | 1.0 ns | 1.0 GHz |
| 8 | 18 | 1.8 ns | 556 MHz |
| 16 | 34 | 3.4 ns | 294 MHz |
| 32 | 66 | 6.6 ns | 152 MHz |
| 64 | 130 | 13.0 ns | 77 MHz |
A 64-bit ripple-carry adder at 100 ps per gate takes 13 ns, which caps the clock at about 77 MHz. Processors run at 3 to 5 GHz. The gap is a factor of 40 to 65, and no amount of tuning closes it. This adder cannot be the one in a fast datapath.
The worst-case input
The domino picture is most exact for a particular input. Take $A = 0111\ldots1$ (that is $2^{N-1} - 1$) and $B = 0000\ldots1$ (that is 1). Bit 0 has $1 + 1$ and generates a carry. Bit 1 has $1 + 0$ plus that carry, and passes it on. So does bit 2, and every bit up to the top. Every internal carry flips from 0 to 1 in sequence, and the top sum bit is the last thing to change. If a register captures the result before the carry has finished travelling, it captures a wrong value, and you have an intermittent timing bug of the kind that takes a day with an oscilloscope to find.
One thing beginners forget is that the final carry-out means something: it says the unsigned result did not fit. $1111 + 0001$ in four bits gives $S = 0000$ with $C_{out} = 1$, and the real answer is 16, which needs five bits. Connect the carry-out somewhere or check it explicitly. Dropping it silently is a common cause of overflow bugs.
When the ripple-carry adder is the right choice
After all that, it is worth saying where this adder is exactly what you want.
Narrow widths. A 4-bit ripple-carry adder is ten gate delays, 1 ns at 100 ps per gate. In a design with a 250 MHz clock and a 4 ns period, that leaves 3 ns to spare. Address decoders, small counters and peripheral registers use adders like this all the time.
FPGAs. This is the important one. Every FPGA family from Xilinx, Intel and Lattice has dedicated carry-chain routing between adjacent logic slices, a fast path that bypasses the lookup tables entirely. A ripple-carry adder mapped onto that chain has a carry delay of 30 to 50 ps per bit, which is as good as or better than a hand-built carry-lookahead adder made of LUTs. On an FPGA you write A + B and let the synthesizer infer the chain. Vivado reports these as CARRY4 or CARRY8 primitives.
Area. Each full adder is the minimum possible hardware per bit. There is no lookahead logic, no duplicated blocks, no selection muxes. When gate count is the binding constraint, as in some very low-power designs, that matters.
Reference designs. It is the clearest implementation of addition, and the one you use to establish correctness before you optimise.
On an ASIC the carry chain of an adder is almost always the critical path, and it is the first thing to look for in a timing report. If the critical path is not through the carry chain, something else in the design is slower than the adder, and that is worth knowing too.
Practice Exercise
Problem 1. A 4-bit ripple-carry adder computes $A + B$ with $A = 1001$ and $B = 0111$. Trace the carries and sums, give the 4-bit result, state whether unsigned overflow occurred, and give the decimal value including the carry-out.
Solution
FA0: $1 + 1 + 0$: $S_0 = 0$, $C_1 = 1$. FA1: $0 + 1 + 1$: $S_1 = 0$, $C_2 = 1$. FA2: $0 + 1 + 1$: $S_2 = 0$, $C_3 = 1$. FA3: $1 + 0 + 1$: $S_3 = 0$, $C_4 = 1$.
The 4-bit result is $0000$ with $C_{out} = 1$, so unsigned overflow occurred. The 5-bit result $10000$ is 16, and $9 + 7 = 16$.
Problem 2. A 32-bit ripple-carry adder has 80 ps gate delays. What is its worst-case delay, the maximum clock it supports, and the speed-up needed to reach 500 MHz?
Solution
$(2 \times 32 + 2) \times 80 \text{ ps} = 5.28$ ns, so $f_{max} \approx 189$ MHz. A 500 MHz clock has a 2 ns period, so the adder must be about $5.28 / 2 = 2.6$ times faster. That is what the next two articles provide.
The problem with this adder is a serial dependency: each carry waits for the one before. Every fast adder is an answer to the question “can we compute a carry without waiting for the previous carry?” The next article gives the first answer, carry lookahead, which computes every carry directly from the inputs.