H-Trees and Balanced Trees

Section 5.1 left you with a clear goal: keep skew small. Section 5.2 is about the shapes that do it, and there are two fundamentally different ways to get there. You can build almost any tree, measure the latency to every leaf, and then add delay wherever a leaf runs early to bring everything into line, a corrective, after-the-fact approach. Or you can pick a shape so symmetric that every leaf is guaranteed the same latency purely by geometry, before you have measured anything. The H-tree is the classic example of the second approach, and it is worth understanding on its own before Section 5.3 shows what a real CTS tool builds, which is usually closer to the first approach but informed by exactly this idea.

The construction

Draw the letter H. Put the clock source at the midpoint of the crossbar. Put a flip-flop at each of the four corners.

Trace the path from the source to any corner. Every path is exactly two segments: one vertical, half the H’s height, and one horizontal, half the H’s width. Because the H is symmetric, top mirroring bottom and left mirroring right, those two lengths are identical for all four corners. Four flops, four geometrically identical paths. No measurement, no correction, no buffer tuning. It is true by construction.

That is the whole trick, and it scales. A real H-tree recurses. Instead of stopping at four leaves, each corner of the outer H becomes the centre of its own smaller H feeding four more leaves: sixteen, then sixty-four, doubling the leaf count and halving the branch length at every level while preserving equal path length throughout. A multi-level H-tree can distribute a clock to thousands of leaves with every root-to-leaf path the same length.

“Balanced tree” is the general category: a clock tree whose branches are built or tuned so every leaf sees equal or near-equal latency. The H-tree is the most geometrically elegant specific way to get balance, because the symmetry does the work. Real CTS tools do not usually draw literal H shapes across an irregular standard cell layout, but “balance branch lengths so leaves see equal latency” is exactly the objective they inherited from this idea. The idea also shows up outside ASIC clocks: FPGA global clock networks and some analogue and RF distribution networks use the same “equality by symmetric geometry” principle wherever arrival time or phase matching matters.

Where it breaks down

Real standard cell designs are not empty grids waiting for a perfect H. They have macros, blockages, uneven flop density and irregular floorplans (Module 3) that a literal H has no clean way to route around. That is the practical limit of pure geometric balancing, and it is exactly the gap that the next article’s alternative, the clock mesh, and Section 5.3’s real TritonCTS algorithm are built to handle.

Practice Exercise

Look at the four-leaf H in the figure. Count the segments from the clock source to FF1, then from the source to FF4. Are the counts the same, and assuming the drawing is to a symmetric scale, are the total lengths the same?

H-trees buy balance through symmetry, but only where the layout is regular enough to support it. The next article looks at the clock mesh, a completely different topology that trades routing resources for skew tightness when a tree, balanced or not, is still not tight enough.