Yield and Process Variation, in Plain Terms

Of the die on the wafer from the last two articles, some come back working perfectly and some do not, from the same masks, the same design and the same nominal process. In this last section of the module we look at why, starting with the two words that describe it: yield and variation.

Yield

Yield is the fraction of manufactured die that work to specification, usually given as a percentage. Every manufacturing process has one, but it is especially unforgiving in semiconductors, where the features are so small that a single particle can ruin a die.

Process variation

No fabricated device matches its model exactly. Gate length, oxide thickness, doping, and wire width and thickness all vary a little: from die to die, wafer to wafer and lot to lot, and even from place to place within one die, through a mix of smooth gradients across the wafer and truly random atomic-scale differences. “Nominal”, the value every report in this course has compared against by default, is a useful and necessary fiction. It is not a promise that any particular device matches it.

Two different kinds of loss are worth separating:

• Random defects. A particle, a local lithography fault or a contamination spot causes an outright failure at one place on the wafer. Their rate is described by a defect density, and it links to the die size discussion in the previous article: a larger die covers more wafer area, so it is more likely to contain at least one defect.
• Parametric variation. Nothing is broken; every transistor works. But the chip as a whole is too slow, too leaky or too power hungry to meet its specification under some real operating condition. This is what the multi-corner signoff of Module 7 exists to bound.

Expected working die

Given a yield and a number of die, the expected number of working die is a multiplication:

$$ E[\text{working die}] = N_{\text{die}} \times Y $$

Taking the 64 die slots from the previous article and an illustrative yield of 70%:

$$ E[\text{working die}] \approx 64 \times 0.70 = 44.8 \approx 45 $$

Neither number is a real SKY130 figure. Real yield depends on the design, its size and how mature the process is.

No real process at any real scale has 100% yield. Design for manufacturability (DFM), the subject of this section, is about pushing that percentage up, not about reaching a variation-free ideal.

A mistake to avoid is treating “my design passed every signoff check” as a yield guarantee. Signoff shows the design works if a fabricated chip falls within the modelled corners. How often real chips actually do, and how often they are hit by a defect, is a manufacturing-statistics question signoff alone cannot answer.

Practice Exercise

A shuttle run gives your project 40 die. Historical yield for this process and this kind of design is about 85%. How many working die should the team plan on, and what should it do differently if it needs at least 30 working chips for a lab kit?

In the next article we look at the specific failure this points to: a design that passes at the typical corner but yields badly across a real population of chips.