RTL to GDSII: ASIC Physical Design with OpenLane & SkyWater
What this course is
The Digital Design and Verilog course ends the moment a design simulates correctly. This course starts there and finishes with a signed-off GDSII file, the handoff artefact a fab consumes. It covers every stage of the RTL-to-GDSII flow: synthesis, floorplanning, placement, clock tree synthesis, routing, timing closure, physical verification and GDSII generation.
This is not a slide-deck course. Every module, starting with Module 1, has you running real tools against real designs: OpenLane, Yosys, OpenROAD, Magic, Netgen and KLayout, targeting the SkyWater SKY130 open-source PDK. You will read real timing reports, real DRC logs and real congestion maps, not idealised textbook examples.
It is written for anyone who has finished, or is comfortable with, RTL design and verification and wants to know what happens to that RTL between “it simulates” and “it is silicon”. No prior physical design experience is assumed, but comfort reading Verilog and using a command line is. The course assumes the RTL fluency built in Digital Design & Verilog; several of the projects reuse designs from that course’s own projects, the UART, the ALU and the RISC core, so their physical design problems are grounded in RTL you may already know.
Course map
Modules
Module 1: The Physical Design Landscape
The open-source EDA stack, the SkyWater SKY130 PDK, and a first complete OpenLane run: a design pushed through every flow stage before any single stage is explained.
| Section | Topics |
|---|---|
| 1.1 The Complete ASIC Flow | Front-end vs. back-end, the abstraction stack, why physical design isn’t optional |
| 1.2 The Open-Source EDA Stack | Yosys, OpenROAD, Magic, Netgen, KLayout, OpenLane as orchestrator |
| 1.3 The SkyWater SKY130 PDK | PDK contents, process specifics, standard cell library variants |
| 1.4 Environment Setup (hands-on) | Installing OpenLane and the PDK, running a first design end to end |
| 1.5 Flow Configuration (hands-on) | config.json anatomy, interactive vs. autonomous flow execution |
Module 2: Logic Synthesis
RTL-to-gates translation revisited for its physical consequences: synthesis strategies, standard cell views, and the first real synthesis run of the course’s reference designs.
| Section | Topics |
|---|---|
| 2.1 From RTL to Gates | Technology mapping, why RTL style has physical consequences |
| 2.2 Yosys in OpenLane (hands-on) | Synthesis strategies, running and comparing area vs. delay mapping |
| 2.3 Standard Cell Views | Liberty timing, LEF, drive strength variants |
| 2.4 Synthesis Constraints (hands-on) | Writing a first SDC, clock definitions |
| 2.5 Synthesis Reports (hands-on) | Reading area, cell count, and pre-placement timing |
Module 3: Floorplanning
The first physical decisions: die shape, power grid, I/O placement and macro placement, each built by hand before OpenLane automates it.
| Section | Topics |
|---|---|
| 3.1 Die & Core Area Planning (hands-on) | Utilization, aspect ratio, core-to-die margin |
| 3.2 Power Planning (hands-on) | Power rings, straps, IR drop intuition |
| 3.3 I/O Pin Placement (hands-on) | Pin order, pad-limited vs. core-limited designs |
| 3.4 Macro Placement (hands-on) | Halos, blockages, orientation |
| 3.5 The OpenLane Floorplan Stage (hands-on) | FP_CORE_UTIL, tap/endcap insertion, viewing the floorplan |
Module 4: Placement
Turning a flat netlist into a legal, row-based layout: global placement, legalization, congestion, and the tuning loop every real flow depends on.
| Section | Topics |
|---|---|
| 4.1 Global Placement | Wirelength, congestion, and timing as competing objectives |
| 4.2 Detailed Placement & Legalization (hands-on) | Running global and detailed placement |
| 4.3 Placement-Driven Timing (hands-on) | Reading pre-CTS timing reports |
| 4.4 Congestion Analysis (hands-on) | Generating and reading a congestion heatmap |
| 4.5 Placement Configuration (hands-on) | Tuning PL_TARGET_DENSITY, iterating |
Module 5: Clock Tree Synthesis
Distributing one clock to thousands of flip-flops without destroying the setup margin: skew, topologies, TritonCTS, and the hold violations that only appear after CTS.
| Section | Topics |
|---|---|
| 5.1 The Clock Distribution Problem | Skew, clock latency |
| 5.2 Clock Tree Topologies | H-tree, clock mesh, buffer insertion |
| 5.3 CTS Algorithms (hands-on) | Running TritonCTS |
| 5.4 Post-CTS Timing (hands-on) | Reading and fixing post-CTS hold violations |
| 5.5 Clock Gating & CTS (hands-on) | CTS on a design with gated clock domains |
Module 6: Routing
From coarse global routes to exact, DRC-legal wires on real metal: the SKY130 stack, special-net routing, and what to do when a design will not route.
| Section | Topics |
|---|---|
| 6.1 Global Routing | Routing grid, SKY130 metal stack |
| 6.2 Detailed Routing (hands-on) | Running TritonRoute |
| 6.3 SKY130 Routing Rules | Spacing, width, antenna rules previewed |
| 6.4 Special Net Routing (hands-on) | Power/ground and clock net routing |
| 6.5 Routability & Iteration (hands-on) | Fixing a routing congestion failure |
Module 7: Timing Closure & Static Timing Analysis
Verifying timing against extracted parasitics: parasitic extraction, multi-corner OpenSTA analysis, ECOs, and signoff timing.
| Section | Topics |
|---|---|
| 7.1 STA Fundamentals, Revisited | Setup/hold with real wire delay |
| 7.2 Parasitic Extraction (hands-on) | Generating and reading a SPEF |
| 7.3 OpenSTA in OpenLane (hands-on) | Multi-corner, multi-mode reports |
| 7.4 Fixing Timing Violations (hands-on) | ECO buffer insertion, gate sizing |
| 7.5 Signoff Timing (hands-on) | Running all signoff corners |
Module 8: Physical Verification
The complete set of checks a layout must pass regardless of simulation or timing results: DRC, LVS, antenna rules, IR drop, and fill.
| Section | Topics |
|---|---|
| 8.1 Design Rule Checking (hands-on) | Running Magic DRC, fixing a real violation |
| 8.2 Layout vs. Schematic (hands-on) | Running Netgen, diagnosing a mismatch |
| 8.3 Antenna Rules (hands-on) | Finding and fixing an antenna violation |
| 8.4 Electrical Checks & IR Drop (hands-on) | Power grid verification |
| 8.5 Fill Insertion (hands-on) | Metal fill, density rule compliance |
Module 9: GDSII Generation and Tapeout
Turning a verified layout into the file a fab consumes: GDS streaming, independent KLayout review, the full signoff checklist, and what happens after tapeout.
| Section | Topics |
|---|---|
| 9.1 GDSII Streaming (hands-on) | Streaming out and inspecting a real GDS |
| 9.2 KLayout Review (hands-on) | Independent layout/netlist cross-checking |
| 9.3 Signoff Checklist (hands-on) | Assembling a complete signoff report |
| 9.4 Preparing for Fabrication | Open shuttle programs, mask generation, wafer fab |
| 9.5 DFM Considerations | Yield, process variation, corner-based design |
Module 10: Capstone Projects
Five full physical design projects, RTL to signed-off GDSII, each forcing a different class of physical design problem, several reusing designs from the Digital Design & Verilog course’s own projects.
| Project | Focus |
|---|---|
| Project 1, Combinational ALU | A clean first full run of the entire flow, no clock or macro complications |
| Project 2, UART Controller | Clock tree synthesis and timing closure on a real sequential design |
| Project 3, SRAM Macro Integration | Macro-aware floorplanning, placement, and routing |
| Project 4, RISC Core, Full Chip | Every module’s discipline, applied to the hardest design in the course |
| Project 5, Debugging a Broken Flow | Diagnosing seeded DRC, LVS, and timing violations from reports alone |
Start with From RTL to Silicon.
Every article in this course runs against free, open-source tools (OpenLane, Yosys, OpenROAD, Magic, Netgen and KLayout) and the SkyWater SKY130A PDK. No paid EDA licence is needed to follow along.