Module 1: The Physical Design Landscape
A Verilog module that passes every testbench is not a chip. It is a description of intent: correct behaviour, in a language a synthesizer can read, with no size, no shape, no wires and no silicon under it. Physical design is everything between that description and a file a fab can manufacture: turning gates into placed cells, placed cells into routed wires, and routed wires into polygons on mask layers.
This module does not explain any single stage in depth; that is the rest of the course. It does two things. It introduces the open-source tools the course runs on (Yosys, OpenROAD, Magic, Netgen and KLayout, driven by OpenLane) and the SkyWater SKY130 process we target, and then it has you run a complete design through the default flow from start to finish, so that every later module has something concrete to point back at.
Every hands-on section in the course assumes a working OpenLane and SKY130 install. Section 1.4 walks through that setup from nothing. Do it before moving to Module 2.
Sections
| Section | Topics |
|---|---|
| 1.1 The Complete ASIC Flow | Front-end versus back-end, the abstraction stack, why physical design decisions are not optional |
| 1.2 The Open-Source EDA Stack | Yosys, OpenROAD, Magic, Netgen, KLayout, and OpenLane as orchestrator |
| 1.3 The SkyWater SKY130 PDK | What a PDK contains, SKY130 process specifics, standard cell library variants |
| 1.4 Environment Setup (hands-on) | Installing OpenLane and the PDK, the directory structure, a first end-to-end run |
| 1.5 Flow Configuration (hands-on) | config.json, the ordered flow stages, interactive versus autonomous execution |
Start with From RTL to Silicon.