Why Placement Already Affects Timing

Section 4.3 opens with a fact that surprises people the first time they hear it. You can get a meaningful timing report on a design with zero routed wires. Not a rough guess or a placeholder, but a real STA run with real path analysis, using cell delays straight from the Liberty file and wire delays estimated from something that already exists at this point in the flow: the physical distance between placed cells.

That works because wire delay is fundamentally a resistance and capacitance story, and both scale with length. A longer wire has more metal, so more resistance, and more area coupling to its neighbours and the substrate, so more capacitance. You do not need the exact routed shape to get a reasonable first estimate of its RC. You need its length, and placement already tells you that, through the same Manhattan distance you have been computing all module.

The Elmore intuition

A simplified, Elmore-style model of wire delay is

$$t_{\text{wire}} \approx 0.69 \cdot R_{\text{wire}} \cdot C_{\text{wire}}$$

Since both (R_{\text{wire}}) and (C_{\text{wire}}) grow in proportion to length (L), the product grows roughly with (L^2). Quadratically, not linearly. That is the one thing to take from this article: doubling a net’s placement distance does not double its wire delay contribution, it roughly quadruples it. This is exactly why placers are so obsessive about wirelength on timing-critical nets specifically, and why the net weighting of Section 4.1 exists. A long critical net is not a bit worse. It is disproportionately worse.

At this point in the flow, after placement and before CTS or routing, OpenROAD estimates parasitics directly from placement geometry with a command like estimate_parasitics -placement. It is necessarily an approximation, since real routed wires bend around obstacles and do not always take the shortest Manhattan path, but it is a useful one. It catches a badly placed critical path before you spend hours on CTS and routing for a design that was never going to meet timing.

This is the deep reason placement and timing closure are not separate, sequential concerns in a real flow. They are intertwined from the first stage that has any physical information at all. A path that looked fine in synthesis-stage STA back in Module 2, with zero wire delay assumed, can look very different the moment placement gives it a real length.

Ranking the risk

Three nets on alu8, with their placement-time Manhattan distances:

Using the quadratic intuition, estimate each net’s wire delay risk relative to net_A as the baseline:

• net_A: 12 um, baseline, 1x
• net_C: 24 um, twice the distance, roughly ((24/12)^2 = 4)x the wire delay
• net_B: 48 um, four times the distance, roughly ((48/12)^2 = 16)x the wire delay

net_B, the carry chain segment, is not just the longest net. By this scaling it carries something like sixteen times the wire delay risk of the shortest net for only four times the distance. Carry chains are often on the critical path, since they are the longest combinational chain in an adder, so this is exactly the kind of net Section 4.1’s timing-driven weighting exists to protect.

Do not treat the (L^2) scaling as a formula for signoff-quality delay. It is an intuition builder. Real wire delay depends on the metal layer, the routed shape, coupling to neighbouring nets and more. What transfers to real designs is the qualitative shape: long nets are disproportionately risky.

Practice Exercise

A net’s placement distance is 16 um and it is not currently on any critical path. A later placement iteration moves nearby cells and stretches it to 32 um. Using the (L^2) intuition, roughly how many times worse is its estimated wire delay after the change?

Physical distance gives placement-stage timing analysis something real to chew on. The next article puts that into practice by reading an actual pre-CTS OpenSTA report for alu8, and paying close attention to the one number in it that is still completely fake.