Running Global and Detailed Placement

Everything so far in this module has been concept and hand arithmetic. Time to run the real thing. This article carries alu8, the 8-bit ALU with a registered output that has been the reference design since Module 2’s synthesis and Module 3’s floorplan, through OpenLane’s placement stage on the floorplan DEF Module 3 produced.

Picking up where the floorplan left off

From Module 3, alu8 synthesised to roughly 1,860 sky130_fd_sc_hd cells and was floorplanned at FP_CORE_UTIL = 45 into a square core about 168 um on a side. That floorplan DEF has row structure, power rings and straps, and I/O pins already placed, but every standard cell in it is still unplaced, sitting wherever the netlist reader happened to drop it. Placement decides where those 1,860 cells go.

Using OpenLane’s interactive Tcl flow, the same environment as the synthesis and floorplan runs in earlier modules:

% package require openlane 0.9
% prep -design alu8 -tag placement_run1
% run_synthesis
% run_floorplan
% run_placement

run_placement is two tool invocations chained under one OpenLane command. OpenROAD’s global_placement (RePlAce, Section 4.1) runs first, followed immediately by detailed_placement (OpenDP, legalisation and flipping, this section). You get one combined report at the end, but the two phases are visible separately in the log.

Reading the log

A representative excerpt of what scrolls by. OpenROAD tags progress messages with the module name, GPL for the global placer and DPL for detailed placement, so the shape below is what you will see even though exact wording varies by version:

[INFO]: Running Global Placement (skip IO)...
[INFO GPL-0002] DBU: 1000
[INFO GPL-0003] Iter: 1     overflow: 0.712   HPWL: 1084302
[INFO GPL-0003] Iter: 20    overflow: 0.401   HPWL: 891447
[INFO GPL-0003] Iter: 40    overflow: 0.183   HPWL: 831960
[INFO GPL-0003] Iter: 61    overflow: 0.098   HPWL: 812394
[INFO GPL-0004] Global placement converged (overflow < 0.10).

[INFO]: Running Detailed Placement...
[INFO DPL-0001] Total cells: 1860
[INFO DPL-0002] Total displacement: 4821.3 dbu
[INFO DPL-0003] Max displacement: 38.5 dbu
[INFO DPL-0004] Legalization: 0 overlaps remaining.
[INFO]: Placement complete. Final HPWL: 818210 dbu

The placement summary

OpenLane writes a summary alongside the DEF. For this run:

The last row is the one I check first, always. Zero remaining overlaps means legalisation fully succeeded. If that number were nonzero, nothing downstream would be trustworthy, because physically impossible cell positions would still be in the design.

On units: SKY130’s DEF convention is UNITS DISTANCE MICRONS 1000, so 1000 database units (dbu) equal one micron. A max displacement of 38.5 dbu is 0.0385 um, an unremarkable legalisation nudge and not a red flag. Get comfortable doing that conversion in your head. Every OpenROAD report speaks in dbu, and every intuition you have about whether a number is big speaks in microns.

Opening the real layout

Up to Module 3, opening a floorplan DEF in a viewer showed an empty core outline, power rings, straps and I/O pins, and no standard cells, because none had been placed. Now there is something inside the core:

% magic -rcfile sky130A.magicrc -T sky130A.tech alu8.placement.def

Zoom into the core and you see, for the first time in this course, real rows of real standard cells: small rectangles packed edge to edge along horizontal rows, alternating orientation exactly as the previous article described, sitting inside but not yet connected by the power straps from Module 3. No routing exists yet; that is Module 6. What you are looking at is purely the placement result, 1,860 real cell footprints, each legally seated on a row with real pin locations, connected only by implied nets so far. KLayout gives the same view with different navigation. Load the same DEF alongside the SKY130 layer map and you get identical geometry, which makes a useful cross-check between the two tools.

Do not be alarmed that there is no routing. Cells have locations; nets do not yet have wires. Confusing “not yet routed” with “broken” is one of the commonest early confusions when looking at layout views mid-flow.

Practice Exercise

The report above shows max displacement of 38.5 dbu. Suppose a different run of the same design reported 2,150 dbu instead. Convert that to microns and say whether that number, on its own, is worth investigating before moving on to CTS.

Placement is legal and visible. But legal says nothing about timing, and it turns out placement already has a strong opinion about your clock period, well before a clock tree or a single route exists. That is Section 4.3.