Project 1, Part 2: Floorplan Through Routing, Back to Back

In the previous article we configured the ALU and synthesised it into 163 cells. A netlist that small could almost be placed by hand. We will not do that. The point of this article is to watch the automated stages run on a design so simple that nothing should go wrong, so that when something does go wrong two projects from now, you already know what normal looks like at each stage. Figure 1 shows the stages we are about to run.

The flow stages for the ALU — Figure 1: Every stage of the flow runs on the ALU except CTS, which has no clock to build a tree for

Run the rest of the flow from where synthesis stopped:

openlane --flow Classic --run-tag alu8_run1 --from OpenROAD.Floorplan designs/alu8/config.json

Each step writes its own log in the run directory. Below are the lines worth reading from each, trimmed.

Floorplan

With relative sizing, OpenLane sizes the core from the synthesised area and FP_CORE_UTIL: about 1,960 µm² of cells at 35% gives a core of about 5,600 µm², roughly 75 µm on a side. The floorplan step then creates the rows and inserts tap and end cap cells, as in Module 3:

Core area: 74.980 x 74.800 um
Number of rows: 27
Tap cells inserted: 54

Nothing remarkable, and that is the point. 27 rows for 163 cells at 35% is roomy, chosen so that density is not a variable you need to think about in this project. Compare it later with Project 4’s floorplan, where utilisation has real consequences.

Placement

Global placement spreads the cells over the rows to minimise wirelength, then detailed placement puts every cell on a legal site, the two-phase process from Module 4:

[INFO GPL-1001] ... final overflow 0.098, HPWL 4041 um
[INFO DPL-0001] Placed 163 instances
Max displacement: 0.92 um

Global placement converged below its overflow target, and legalisation moved no cell by more than a micron. A small, loosely packed design gives the legaliser nothing to argue about. Remember the shape of this report: it is what an uneventful placement looks like.

Clock tree synthesis: nothing to do

RUN_CTS is false, so the CTS step does not run at all, and the flow’s log says it was skipped. Even if it did run, there is no clock net for TritonCTS to build a tree from.

This is the only project in the module where a whole stage disappears, and it is worth being clear why. CTS exists to deliver one clock edge to many flops with a bounded skew. No flops means no skew to bound. Every other project in this module has flops, and from Project 2 onwards this stage is where much of the work happens.

Routing

Global routing assigns every net a coarse path through the routing grid, then detailed routing lays down exact, rule-correct geometry, iterating until no violations remain:

[INFO GRT-0018] Total wirelength: 8214 um
[INFO DRT-0195] Start 0th optimization iteration.
    Completing 100% with 7 violations.
[INFO DRT-0195] Start 1st optimization iteration.
    Completing 100% with 0 violations.
[INFO DRT-0198] Complete detail routing.
Total wire length = 8501 um.

Even a design this easy finishes its first detailed routing pass with a few violations; that is normal, and the router clears them in the next pass. Compare the two wirelengths: 8,214 µm estimated by global routing against 8,501 µm actually routed, a difference of about 3.5%. A gap that small is healthy on an uncongested design. A much larger gap would be the first sign of a router working hard to find its way around.

Practice Exercise

Legalisation moved no cell by more than 0.92 µm. If PL_TARGET_DENSITY had been 0.85 instead of 0.45, would you expect the maximum displacement to go up, down or stay about the same, and why?

Solution

It would very likely go up. Global placement optimises wirelength with cells allowed to overlap a little, and legalisation then moves each cell to the nearest free legal site. At 0.45 target density, global placement spreads the cells out, so there is almost always free space right next to each cell’s ideal position. At 0.85 the cells are packed much closer, a cell’s ideal position is more likely to be taken, and the legaliser has to move it further to find a free site. Density and legalisation displacement go together, which is a first glimpse of the congestion pressure Module 4 covered and this project’s low density avoids.

Floorplan, placement and routing all finished cleanly, and CTS had no work to do. In the next article we run the full set of signoff checks on the ALU, write its signoff report, and look honestly at the problems this simple design never had to face.