Why Synthesis-Stage Timing Is Optimistic

Section 2.2’s comparison reported a worst slack of +5.75 ns for the area-optimised alu8, checked against the SDC from the last two articles. That number is real. OpenSTA computed it against real Liberty arcs on a real netlist. It is also, unavoidably, optimistic. This article runs the same report in full and names what it is missing.

Running synthesis-stage STA on alu8

openlane --flow Classic --run-tag alu8_area designs/alu8/config.json --to Synthesis
sta runs/alu8_area/tmp/synthesis/checks.tcl

The report (illustrative, in the structure of real report_checks output):

Startpoint: b[7] (input port clocked by clk)
Endpoint:   _068_ (result_reg[6], rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type:  max

  Fanout  Cap     Slew    Delay   Time   Description
--------------------------------------------------------------------
                                   0.00   clock clk (rise edge)
                                   0.00   input external delay
                          2.00     2.00   input delay set_input_delay
     4    0.012   0.09    0.18     2.18   sky130_fd_sc_hd__xor2_1 (b[7] -> X)
     2    0.008   0.07    0.14     2.32   sky130_fd_sc_hd__mux2_1 (A0 -> X)
     3    0.010   0.08    0.21     2.53   sky130_fd_sc_hd__o21ai_1 (A -> Y)
     2    0.009   0.06    0.17     2.70   sky130_fd_sc_hd__mux2_1 (A1 -> X)
     1    0.004   0.05    0.09     2.79   sky130_fd_sc_hd__dfxtp_1 (D setup)
                                   2.79   data arrival time

                                  10.00   clock clk (rise edge)
                                   0.00   clock network delay (ideal)
                                  -0.08   library setup time
                                   9.92   data required time
--------------------------------------------------------------------
                                   9.92   data required time
                                  -2.79   data arrival time
--------------------------------------------------------------------
                                   7.13   slack (MET)

This path shows +7.13 ns rather than the headline +5.75 ns. The design has several paths; this report walks one for illustration, and the worst across the design is the +5.75 ns figure from Section 2.2.

Two lines worth staring at

Two lines do a lot of quiet, optimistic work.

0.00   clock network delay (ideal)

This says the clock arrives at every flip-flop’s clock pin at the same instant, with zero delay from the clock port. That is an ideal clock. No clock tree exists yet, because clock tree synthesis (Module 5) has not run. Real silicon has no zero-delay, perfectly simultaneous clock; it has buffers, wire resistance and capacitance between the source and every flop, adding delay and skew (registers receiving the clock at slightly different times).

2    0.008   0.07    0.14     2.32   sky130_fd_sc_hd__mux2_1 (A0 -> X)

That 0.14 ns is computed from cell timing arcs and a wire load model, a statistical estimate of a net’s capacitance based on fanout, not the capacitance of any wire that has been drawn. No placement has happened. No router has run. The tool is estimating, reasonably, but estimating.

What is missing right now

Effect	Present at synthesis-stage STA?	Where it gets added
Real cell delays from Liberty	Yes
Real logical structure (levels of logic)	Yes
Real placement locations	No	Module 4 (Placement)
Real wire parasitics (actual R, C)	No	Module 7 (post-route STA, real extraction)
A real clock tree (buffers, skew)	No	Module 5 (Clock Tree Synthesis)
Crosstalk and signal integrity	No	Module 7 (signoff timing)

None of this makes the +5.75 ns and +7.13 ns useless. The opposite: a design failing timing even under this generous view is essentially guaranteed to fail worse once wire delay and skew are added, so a clean synthesis-stage report is a useful early gate. It is not a finish line. Think of it as a best-case sanity check: it answers “is there any hope this meets timing”, not “will this meet timing in silicon”. Every later module adds one more layer of physical reality on top of this same report format, and you will watch slack shrink, sometimes a lot, as each is added. A design passing with a fraction of a nanosecond at synthesis, before any of the effects in the table are modelled, is not nearly done; it deserves attention now rather than a surprise three modules later.

Practice Exercise

A colleague argues that since synthesis-stage STA uses real Liberty cell delays, it should be treated as close to final signoff, and that Modules 4 to 7 mostly confirm what synthesis showed. Using the table, write a two- or three-sentence rebuttal naming the missing effects.

Solution

Liberty delays capture how fast each gate is; they say nothing about the wires between gates, which do not exist yet as placed, routed geometry. Two effects this stage cannot include by construction are real wire parasitics (synthesis-stage STA uses a statistical wire load model, not the extracted resistance and capacitance of routed wires from Module 7) and a real clock tree (synthesis-stage STA assumes an ideal, zero-delay, zero-skew clock, while Module 5’s clock tree introduces both delay and skew between registers). Both consume slack, and neither is knowable until placement, CTS and routing have happened. Later modules do not confirm synthesis’s numbers; they replace optimistic estimates with physically grounded ones, usually toward less margin.

In the next article, Section 2.5 teaches you to read these reports on your own, starting with the Yosys stats report, line by line.