SYNTH_STRATEGY: Area Versus Delay

The previous article ended on the -script argument to abc. This article is about the config field that chooses it.

Two engineers hand identical RTL to OpenLane. One gets fewer, smaller cells and comfortable but unspectacular timing. The other gets more, bigger cells and noticeably better timing margin. Same tool, same RTL, same library. What changed is almost certainly one field: SYNTH_STRATEGY.

What the knob touches

ABC’s mapping step is invoked with -script $::env(ABC_SCRIPT), a file of ABC commands controlling how it searches for a covering. SYNTH_STRATEGY in config.json selects which of several pre-built ABC scripts OpenLane hands to that argument. Each biases ABC’s cost function differently:

{
  "SYNTH_STRATEGY": "AREA 0"
}

versus

{
  "SYNTH_STRATEGY": "DELAY 1"
}

An AREA strategy tells the mapper: when several legal coverings exist for the same logic (recall the NAND restructuring in the first article of Section 2.1), prefer the one with the smallest total cell area, even at the cost of a somewhat longer path. A DELAY strategy inverts the priority: prefer the covering that minimises delay along the estimated critical path, even if that means larger, higher-drive cells or duplicated logic, accepting more silicon.

Neither direction is free

This is the point to internalise before touching the knob on a real project: SYNTH_STRATEGY is not a “make it better” dial. It is a trade-off dial.

Toward AREA: smaller die area and lower dynamic power (fewer, smaller transistors switching), at the cost of tighter timing margin, closer to violating the constraints or violating them outright on a tight clock.
Toward DELAY: more timing margin, which can rescue a design failing its clock target at synthesis, at the cost of a larger netlist that placement then has more cells to fit and routing more nets to connect, which can make later stages harder even while the synthesis numbers look better.

This is the same area-versus-speed trade every layer of digital design eventually surfaces. RTL pipelining trades area (extra registers) for speed. Gate sizing trades area (bigger transistors) for speed. SYNTH_STRATEGY is the same trade as a config field. A DELAY run’s better timing report is not unconditionally the better result; a design with generous margin but a blown area or power budget has failed a different requirement instead of the one you were looking at.

Setting the field

For alu8, the relevant part of designs/alu8/config.json:

{
  "DESIGN_NAME": "alu8",
  "VERILOG_FILES": "dir::src/alu8.v",
  "CLOCK_PORT": "clk",
  "CLOCK_PERIOD": 10.0,
  "SYNTH_STRATEGY": "AREA 0"
}

Changing that one field to "DELAY 1" and rerunning run_synthesis on identical RTL, constraints and library is exactly the experiment the next article runs end to end: same design, same clock target, two strategies, two reports side by side.

Practice Exercise

A colleague’s design meets timing comfortably with SYNTH_STRATEGY set to "DELAY 2", but the block’s area budget is blown by about 20 percent. They ask whether switching to an AREA strategy is safe. What is the actual risk?

Solution

Switching to AREA is very likely to shrink the netlist and help the budget, but it trades away some of the margin DELAY 2 was providing. That margin came from ABC choosing higher-drive cells and shorter logic chains because delay was prioritised. The risk is that a design comfortably meeting timing under DELAY 2 lands with small positive slack, or a violation, under an AREA strategy on the same RTL and constraints. The right move is to make the switch and then re-check the timing report (Section 2.5 covers how) before treating the area problem as solved, because it may only have been traded for a timing problem.

In the next article we run the experiment: alu8 through synthesis twice, once per strategy, with cell count, area and timing side by side.