The Flow, Stage by Stage

You have now seen the flow from three angles: the stage diagram in Section 1.1, the tool-by-tool breakdown in Section 1.2, and a real run scrolling past in your terminal in Section 1.4. This article consolidates the three into one reference list, the map every remaining module assumes you can place its content against.

The complete stage list

#	Stage	One-sentence job	Course module
1	Synthesis	Map RTL to real standard cells, producing a gate-level netlist	Module 2
2	Floorplan	Fix die and core size, place I/O pins, build the power distribution network	Module 3
3	Placement	Give every standard cell instance a legal (x, y) coordinate	Module 4
4	Clock Tree Synthesis	Build a balanced clock network to every flip-flop	Module 5
5	Global Routing	Plan approximate wire paths and routing resource allocation	Module 6
6	Detailed Routing	Draw exact, DRC-legal metal geometry for every net	Module 6
7	Signoff / Physical Verification	Confirm timing (STA), DRC, LVS, antenna and electrical checks pass	Modules 7 and 8
8	GDS Streamout	Emit the final manufacturable GDSII	Module 9

Global and detailed routing are two steps within one module rather than two modules. That is deliberate: global routing plans approximately where wires go, at coarse resolution, to check feasibility quickly, and detailed routing commits to the exact rule-legal geometry afterwards. They are sequential sub-stages of one routing problem. Every module title from 2 to 9 traces to a row in this table, which is why a later “as covered in Module 5” is a checkable claim.

Read your own run against the table

Go back to the run from Section 1.4 and list its top-level directory:

ls designs/my_first_design/runs/<run-tag>/

For each subfolder (synthesis/, floorplan/, placement/, cts/, routing/, signoff/, or similar depending on your OpenLane version’s naming), match it to a row. You are not inspecting contents yet, that is the rest of the course, only confirming that the abstract list corresponds one to one with folders on your disk produced by a run you executed. If a folder appears that the table does not account for (some versions add bookkeeping folders), that is worth a moment’s curiosity rather than something to ignore. Small confusions are cheaper to resolve on a toy design than mid-debug on something that matters.

The order is a hard dependency chain, not a convention. Each stage’s output is structurally required as the next stage’s input: placement needs a netlist to place, routing needs placed cells to connect. Later modules occasionally show what breaks when a stage is fed the wrong upstream input.

Practice Exercise

Without looking at the table, write the eight stages in order from memory, then check. For any you missed or misordered, explain in one sentence why that stage depends on the one before it.

Solution

The order: synthesis, floorplan, placement, clock tree synthesis, global routing, detailed routing, signoff and physical verification, GDS streamout. The dependencies: synthesis precedes floorplanning because the floorplanner needs a netlist’s cell count and area to size the die; floorplanning precedes placement because placement needs a core area and fixed I/O locations; placement precedes CTS because the clock tree connects to flip-flops at their placed locations; CTS precedes routing because the clock network’s wires must be routed like any other net and the router needs the clock structure finalised; routing precedes signoff because timing, DRC and LVS all need real extracted geometry to check; and streamout is last because it exports the verified, finished layout. Each stage needs a physical artefact only the previous one produces.

In the next article, the last of this module, we introduce interactive mode, running one stage at a time and inspecting outputs in between, and the two commands you will type first when Module 2 begins.