Yosys and OpenROAD
Section 1.1 named the stages. Section 1.2 names the tools.
For most of the history of chip design, the tools that do everything this course covers, synthesis, placement, clock tree synthesis, routing, timing analysis, were closed-source products from a handful of EDA vendors, licensed by the seat at prices out of reach of a hobbyist, a student, or frankly most companies that are not chip companies. Some of those tools are excellent. It is simply a fact that shaped who got to learn this discipline for decades. It is no longer the only option. This course runs entirely on open-source tools implementing the same stages, and the two doing the heaviest lifting are Yosys and OpenROAD.
Yosys: RTL in, gates out
Yosys is a synthesis tool, and that is its whole job. Give it RTL (Verilog, here) and a target standard cell library, and it produces a gate-level netlist: the artefact from the first article of Section 1.1, now expressed as real cell instances from a real library.
Internally Yosys parses the RTL, builds an internal representation of the logic, applies optimisation passes (constant folding, dead-code elimination and more), and hands the final map-to-real-cells step to ABC, a logic synthesis and technology-mapping engine. Module 2 goes into all of this. For now, Yosys is the tool at the first arrow of the flow diagram.
A minimal invocation:
yosys -p "read_verilog design.v; synth; write_verilog synth.v"
Left to right: read_verilog design.v loads the RTL; synth runs the generic synthesis pass (mapping to internal generic gates, before library-specific mapping); write_verilog synth.v writes the netlist out. In the OpenLane flow from Section 1.4 this sequence runs automatically with the SKY130 library swapped in for the mapping step, but the shape, read RTL, synthesize, write netlist, is the shape you will see everywhere from here.
OpenROAD: one tool, several historically separate jobs
Where Yosys does one job, OpenROAD is an umbrella project built to replace a whole sequence of point tools that, in a commercial flow, would be five or more separately licensed products:
| Stage | OpenROAD component |
|---|---|
| Floorplanning | OpenROAD’s floorplan initialization |
| Placement | RePlAce (global placement) + OpenDP (detailed placement, legalization) |
| Clock Tree Synthesis | TritonCTS |
| Global routing | FastRoute |
| Detailed routing | TritonRoute |
| Static timing analysis | OpenSTA |
That is OpenROAD’s own positioning and it is worth taking seriously: one integrated tool covering what used to need several vendor products stitched together, each with its own licence, file formats and quirks at every handoff. OpenROAD’s components pass data to each other in-process rather than through export and import between tools.
OpenSTA, the timing engine, is not only an internal helper. It is the same static timing analysis engine you will invoke by name from Module 7 to check whether the design meets its constraints after real placement and routing. It is used at every stage from here on that needs a real timing answer.
One thing to put aside now: “open source” does not mean toy. OpenROAD and Yosys are used in real, fabricated chips, including the SKY130 designs this course builds toward. Open source here means the source is available and the tools are free to use, not that they are less capable.
Practice Exercise
Given the yosys -p "read_verilog design.v; synth; write_verilog synth.v" command, what would you change if you wanted Yosys to also print a summary of resource usage (cell counts, gate types) before writing the netlist? Describe conceptually what needs to happen and where in the sequence it goes.
Solution
A reporting step has to come after synthesis (so there is something to report on) and the sequence should still end by writing the netlist, since that is what the rest of the flow depends on. Conceptually: read the RTL, run synth, run a statistics pass (Yosys has a stat command that prints cell type counts and totals), then write the netlist. The general point: Yosys command sequences are a pipeline of named passes executed in order, and inserting a step means inserting it at the right point in that left-to-right sequence, the same ordered-pipeline pattern every OpenLane stage follows.
In the next article we meet the tools on the other side of the flow, Magic, Netgen and KLayout, which see and independently check the layout that Yosys and OpenROAD produce.