Module 9: SystemVerilog for Design & Verification
Every line of Verilog since Module 4 has been Verilog-2001, the standard and the style that has been the backbone of this course. It is also still what a large amount of real RTL looks like. But it is not the whole picture. SystemVerilog extended the language in two directions at once: cleaner, more explicit constructs for design, and an entirely new set of constructs (classes, randomization, assertions) built for verification, going well past what a hand-written self-checking testbench from Module 6 can practically do.
This module is not a second language course. It is a deliberately scoped bridge. By the end you will recognise every SystemVerilog construct you are likely to meet in a modern codebase, and you will have written enough of each to know what problem it solves, not only what its syntax looks like.
Section 9.1 stays on the design side: everything in it is a cleaner, safer way to write RTL concepts you already know from Modules 4 and 5. Section 9.2 crosses into new territory, verification built from classes and randomized, constrained stimulus rather than the directed tests of Module 6. Section 9.3 closes with assertions, a way to state “this should always be true” or “this sequence of events should always happen this way” directly and have the simulator check it continuously.
Objectives by section
| Section | You will be able to |
|---|---|
| 9.1 Design Enhancements | Write logic-typed signals, use always_ff/always_comb/always_latch to make design intent explicit and checkable, model structured data with typedef/struct/enum, and clean up multi-signal module interfaces with interface/modport |
| 9.2 Verification Basics | Build a basic testbench component as a SystemVerilog class, generate randomized stimulus with rand/randc, constrain that randomization to legal values, and recognize the shape of a UVM-ready testbench architecture |
| 9.3 Assertions (SVA) | Write immediate assertions for simulation-time checks, write concurrent assertions describing multi-cycle temporal behavior, and read/write a basic property and sequence |
Estimated time
| Section | Posts | Reading and exercise time |
|---|---|---|
| 9.1 SystemVerilog Design Enhancements | 4 | ~52 minutes |
| 9.2 SystemVerilog Verification Basics | 4 | ~56 minutes |
| 9.3 Assertions (SVA) | 3 | ~42 minutes |
| Total | 11 | ~150 minutes |
Section 9.1 opens with the most immediately useful change in SystemVerilog: one type, logic, that ends the wire-versus-reg confusion Section 4.2 warned about. It does not change what the hardware does. It changes how much you have to think about a distinction that was never really about hardware. Start with 9.1 SystemVerilog Design Enhancements.