https://circuit.quest/courses/rtl-to-gds-openlane/module-01/ Recent content in Module 1: The Physical Design Landscape on Circuit Quest Hugo en-us Mon, 14 Sep 2026 00:00:00 +0000 https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-01-flow-overview/01-from-rtl-to-silicon/ Mon, 14 Sep 2026 00:00:00 +0000 https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-01-flow-overview/01-from-rtl-to-silicon/ A design that passes every testbench is a description of correct behaviour, not a chip. This article draws the line between front-end verification and everything physical design still has to do. https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-01-flow-overview/02-the-abstraction-stack/ Mon, 14 Sep 2026 00:00:00 +0000 https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-01-flow-overview/02-the-abstraction-stack/ The same design is described five different ways on its way to silicon: RTL, gates, placed and routed layout, mask polygons, transistors. Each layer exists to answer a question the others cannot. https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-01-flow-overview/03-why-physical-design-is-not-optional/ Mon, 14 Sep 2026 00:00:00 +0000 https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-01-flow-overview/03-why-physical-design-is-not-optional/ Timing closure, area, power and yield are not RTL-level concerns. They are where a functionally perfect design goes to fail, and this course exists to prevent that. https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-02-open-source-eda-stack/01-yosys-and-openroad/ Mon, 14 Sep 2026 00:00:00 +0000 https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-02-open-source-eda-stack/01-yosys-and-openroad/ Yosys turns RTL into gates; OpenROAD turns gates into a routed, timed layout. Together they are the computational core the course runs on, and both are open source. https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-02-open-source-eda-stack/02-magic-netgen-and-klayout/ Mon, 14 Sep 2026 00:00:00 +0000 https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-02-open-source-eda-stack/02-magic-netgen-and-klayout/ Magic edits and checks layout, Netgen confirms the layout matches the netlist, and KLayout independently verifies both. Their overlap is a signoff discipline, not redundancy. https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-02-open-source-eda-stack/03-openlane-as-orchestrator/ Mon, 14 Sep 2026 00:00:00 +0000 https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-02-open-source-eda-stack/03-openlane-as-orchestrator/ OpenLane does no physical design step itself. It is the scripted glue that runs Yosys, OpenROAD, Magic, Netgen and KLayout in the right order with the right files handed between them. https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-03-sky130-pdk/01-what-a-pdk-contains/ Mon, 14 Sep 2026 00:00:00 +0000 https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-03-sky130-pdk/01-what-a-pdk-contains/ A PDK is a fab’s own description of what its process can build and how to describe a design targeting it: SPICE models, multi-view standard cell libraries, and DRC and LVS rule decks, in one package. https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-03-sky130-pdk/02-sky130-process-specifics/ Mon, 14 Sep 2026 00:00:00 +0000 https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-03-sky130-pdk/02-sky130-process-specifics/ SKY130 is a real, fabricable, mixed-signal 130 nm process with an open rule deck: a genuine node, not a toy, which is what makes it a realistic teaching target. https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-03-sky130-pdk/03-standard-cell-library-variants/ Mon, 14 Sep 2026 00:00:00 +0000 https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-03-sky130-pdk/03-standard-cell-library-variants/ SKY130 ships the same logical cell set laid out and characterised several ways, hd, hs, ls and more, each a different area, speed and power trade, selected with one config line. https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-04-environment-setup/01-installing-openlane-and-the-pdk/ Mon, 14 Sep 2026 00:00:00 +0000 https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-04-environment-setup/01-installing-openlane-and-the-pdk/ A hands-on install of OpenLane through Docker and the SKY130 PDK through Volare, pinned to a known version, and why that pin is not optional. https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-04-environment-setup/02-the-openlane-directory-structure/ Mon, 14 Sep 2026 00:00:00 +0000 https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-04-environment-setup/02-the-openlane-directory-structure/ A tour of the OpenLane directory tree, where designs live, where the PDK is, and where run outputs land, ending with a first design folder built by hand. https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-04-environment-setup/03-running-your-first-design-end-to-end/ Mon, 14 Sep 2026 00:00:00 +0000 https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-04-environment-setup/03-running-your-first-design-end-to-end/ The payoff: run a small counter through the complete, unmodified OpenLane flow with one command, watch every stage go by, and find the GDSII waiting at the end. https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-05-flow-configuration/01-anatomy-of-a-design-config/ Mon, 14 Sep 2026 00:00:00 +0000 https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-05-flow-configuration/01-anatomy-of-a-design-config/ A field-by-field walk through a real config.json for the Module 1 counter: what each field does now, and which module teaches you to tune the ones that matter. https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-05-flow-configuration/02-the-ordered-flow-stages/ Mon, 14 Sep 2026 00:00:00 +0000 https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-05-flow-configuration/02-the-ordered-flow-stages/ The complete ordered list of every stage OpenLane runs, one sentence each, mapped to the module that teaches it in depth: the reference map for the rest of the course. https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-05-flow-configuration/03-interactive-vs-autonomous-flow-execution/ Mon, 14 Sep 2026 00:00:00 +0000 https://circuit.quest/courses/rtl-to-gds-openlane/module-01/01-05-flow-configuration/03-interactive-vs-autonomous-flow-execution/ OpenLane’s interactive Tcl mode runs one stage at a time and lets you inspect real inputs and outputs between steps. It is the mode this course uses from Module 2 on, and here is why.