https://circuit.quest/courses/digital-design-verilog/module-10/ Recent content in Module 10: Capstone Projects on Circuit Quest Hugo en-us Mon, 01 Jun 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-10/10-01-risc-processor-core/01-instruction-set-and-architecture/ Mon, 01 Jun 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-10/10-01-risc-processor-core/01-instruction-set-and-architecture/ Every processor design starts with a decision that has nothing to do with gates: what can this machine do? Get the instruction set wrong and no amount of clever RTL saves you. A minimal, complete 8-bit ISA, designed deliberately. https://circuit.quest/courses/digital-design-verilog/module-10/10-01-risc-processor-core/02-datapath-design/ Mon, 01 Jun 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-10/10-01-risc-processor-core/02-datapath-design/ The datapath for this processor is not new hardware. It is the ALU from Module 2, the register file from Module 3 and the memory model from Module 7, wired together the way the ISA from the previous article requires. https://circuit.quest/courses/digital-design-verilog/module-10/10-01-risc-processor-core/03-control-unit-and-fsm/ Mon, 01 Jun 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-10/10-01-risc-processor-core/03-control-unit-and-fsm/ Every mux select the previous article left undriven becomes one output of one FSM, in the two-block style from Section 5.6. This is where fetch, decode and execute stop being three words in a spec and become three states. https://circuit.quest/courses/digital-design-verilog/module-10/10-01-risc-processor-core/04-full-implementation-and-testbench/ Mon, 01 Jun 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-10/10-01-risc-processor-core/04-full-implementation-and-testbench/ Datapath and control unit wired into one processor, then the hardest part of any processor project: proving it is right, by checking its results against an independent software model of the same program rather than by eyeballing a waveform. https://circuit.quest/courses/digital-design-verilog/module-10/10-02-uart-controller/01-uart-protocol-and-specification/ Mon, 01 Jun 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-10/10-02-uart-controller/01-uart-protocol-and-specification/ UART is the protocol referenced constantly since Module 3 without its timing ever being pinned down. Before any RTL, this article does that: frame format, bit timing, and the edge cases a real implementation has to handle. https://circuit.quest/courses/digital-design-verilog/module-10/10-02-uart-controller/02-baud-rate-generator/ Mon, 01 Jun 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-10/10-02-uart-controller/02-baud-rate-generator/ One parameterized modulo-N counter from Section 3.5, sized to turn a system clock into UART bit timing, and for the receiver a second tick running 16 times faster to give the centre-sampling strategy real resolution. https://circuit.quest/courses/digital-design-verilog/module-10/10-02-uart-controller/03-transmitter-and-receiver-fsms/ Mon, 01 Jun 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-10/10-02-uart-controller/03-transmitter-and-receiver-fsms/ The transmitter is the Section 3.4 PISO shift register wearing a UART frame. The receiver is the harder half: an FSM that has to find a start bit it was never told was coming, then sample eight data bits with no shared clock to help. https://circuit.quest/courses/digital-design-verilog/module-10/10-02-uart-controller/04-full-implementation-and-testbench/ Mon, 01 Jun 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-10/10-02-uart-controller/04-full-implementation-and-testbench/ Wire the transmitter’s output to the receiver’s input, send a byte, and check what comes out. Simple to describe, and exactly the kind of test that benefits from Module 9’s randomization to build real confidence rather than proving one lucky byte works. https://circuit.quest/courses/digital-design-verilog/module-10/10-03-spi-master-controller/01-spi-protocol-and-modes/ Mon, 01 Jun 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-10/10-03-spi-master-controller/01-spi-protocol-and-modes/ UART avoided a shared clock and paid for it with fragile timing. SPI shares a clock and gets solid timing in return, but that clock has two independent configuration choices, and getting either wrong means both sides sample garbage. https://circuit.quest/courses/digital-design-verilog/module-10/10-03-spi-master-controller/02-shift-register-datapath-and-cs/ Mon, 01 Jun 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-10/10-03-spi-master-controller/02-shift-register-datapath-and-cs/ SPI transmits and receives at the same time, every clock edge, which means one shift register, wired the right way, does the work Section 3.4 split across separate PISO and SIPO structures for UART. https://circuit.quest/courses/digital-design-verilog/module-10/10-03-spi-master-controller/03-full-implementation-and-testbench/ Mon, 01 Jun 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-10/10-03-spi-master-controller/03-full-implementation-and-testbench/ The controller FSM that generates SCLK for whichever CPOL/CPHA combination is configured, and a loopback test that proves all four modes independently, because a test that checks one mode has verified a quarter of the claim. https://circuit.quest/courses/digital-design-verilog/module-10/10-04-sram-controller/01-sram-timing-and-specification/ Mon, 01 Jun 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-10/10-04-sram-controller/01-sram-timing-and-specification/ The first project where the datapath, the memory itself, is simple, and the whole engineering challenge is timing discipline: reading a memory datasheet’s setup and hold demands and translating them, correctly, into an FSM’s cycle count. https://circuit.quest/courses/digital-design-verilog/module-10/10-04-sram-controller/02-address-decoding-and-fsm/ Mon, 01 Jun 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-10/10-04-sram-controller/02-address-decoding-and-fsm/ Every other FSM in this course sequenced distinct operations. This one is unusual in an instructive way: most of its states exist to count cycles, enforcing the datasheet timing from the previous article. https://circuit.quest/courses/digital-design-verilog/module-10/10-04-sram-controller/03-full-implementation-and-testbench/ Mon, 01 Jun 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-10/10-04-sram-controller/03-full-implementation-and-testbench/ A memory model that always returns correct data, however early you read it, lets a broken controller pass every test. This article builds the alternative: a model that returns X if you cheat, and a testbench that confirms the controller never does. https://circuit.quest/courses/digital-design-verilog/module-10/10-05-axi4-lite-slave/01-axi4-lite-protocol-basics/ Mon, 01 Jun 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-10/10-05-axi4-lite-slave/01-axi4-lite-protocol-basics/ Every bus protocol in real SoC design descends from the idea introduced here: independent, decoupled ready/valid channels rather than one monolithic transaction. AXI4-Lite is where you meet it in its standardized form. https://circuit.quest/courses/digital-design-verilog/module-10/10-05-axi4-lite-slave/02-register-file-and-handshake-fsm/ Mon, 01 Jun 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-10/10-05-axi4-lite-slave/02-register-file-and-handshake-fsm/ The register file behind this interface is nothing new: Section 3.6’s storage, addressed and gated by the five-channel handshake logic Part 1 specified. The new engineering is managing five channels’ worth of state at once. https://circuit.quest/courses/digital-design-verilog/module-10/10-05-axi4-lite-slave/03-full-implementation-and-testbench/ Mon, 01 Jun 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-10/10-05-axi4-lite-slave/03-full-implementation-and-testbench/ The complete AXI4-Lite slave, verified with a directed test, a randomized independent-timing test, and a concurrent assertion checking the ordering rule from Part 1. Then a look back over what ten modules built toward.