https://circuit.quest/courses/digital-design-verilog/module-09/ Recent content in Module 9: SystemVerilog for Design & Verification on Circuit Quest Hugo en-us Mon, 18 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-09/09-01-systemverilog-design/01-the-logic-type/ Mon, 18 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-09/09-01-systemverilog-design/01-the-logic-type/ Section 4.2 called wire versus reg the most confusing part of classic Verilog. SystemVerilog’s answer was not a better explanation but a single new type that makes the distinction mostly irrelevant. https://circuit.quest/courses/digital-design-verilog/module-09/09-01-systemverilog-design/02-always-ff-comb-and-latch/ Mon, 18 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-09/09-01-systemverilog-design/02-always-ff-comb-and-latch/ Plain always never told the tool what you meant to build, only what you wrote. These three blocks tell it both, and let it catch the gap at compile time instead of at synthesis time. https://circuit.quest/courses/digital-design-verilog/module-09/09-01-systemverilog-design/03-typedef-struct-union-enum/ Mon, 18 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-09/09-01-systemverilog-design/03-typedef-struct-union-enum/ Every FSM since Module 5 has used localparam to name states as bit patterns. enum names them as names, and struct groups related signals together so a bus does not have to be a loose pile of same-width wires. https://circuit.quest/courses/digital-design-verilog/module-09/09-01-systemverilog-design/04-interfaces-and-modports/ Mon, 18 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-09/09-01-systemverilog-design/04-interfaces-and-modports/ A ready/valid handshake is four or five signals that always travel together, in every module that uses it. An interface makes that grouping a declared thing, and a modport says which way each signal goes for each side of the connection. https://circuit.quest/courses/digital-design-verilog/module-09/09-02-systemverilog-verification/01-classes-and-objects-for-verification/ Mon, 18 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-09/09-02-systemverilog-verification/01-classes-and-objects-for-verification/ Every testbench since Module 6 has been hardware describing hardware: modules, wires, always blocks. A SystemVerilog class is something different, software describing test data, and it is why verification code stops looking like design code. https://circuit.quest/courses/digital-design-verilog/module-09/09-02-systemverilog-verification/02-randomization-with-rand-and-randc/ Mon, 18 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-09/09-02-systemverilog-verification/02-randomization-with-rand-and-randc/ Directed tests since Module 6 have used hand-picked inputs to exercise specific behaviour. Randomization turns that around: let the tool generate thousands of legal inputs, and let volume find the corner cases nobody thought to write. https://circuit.quest/courses/digital-design-verilog/module-09/09-02-systemverilog-verification/03-constraints-and-constraint-solving/ Mon, 18 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-09/09-02-systemverilog-verification/03-constraints-and-constraint-solving/ Plain rand does not know that an opcode field has only 6 legal values out of 8, or that two fields need a relationship between them. constraint blocks tell the randomization engine exactly that, and turn raw randomization into something usable. https://circuit.quest/courses/digital-design-verilog/module-09/09-02-systemverilog-verification/04-toward-a-uvm-ready-testbench/ Mon, 18 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-09/09-02-systemverilog-verification/04-toward-a-uvm-ready-testbench/ Transactions, randomization and constraints are the pieces. This article assembles them into an architecture, driver, monitor and scoreboard, the shape every UVM testbench takes, built here without UVM so the structure is plain to see. https://circuit.quest/courses/digital-design-verilog/module-09/09-03-assertions-sva/01-immediate-assertions-in-systemverilog/ Mon, 18 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-09/09-03-assertions-sva/01-immediate-assertions-in-systemverilog/ You have been writing if-statement checks with $display and $error since Module 6. assert is the same idea, purpose-built, and it changes where a check can live: out of the testbench and into the design itself. https://circuit.quest/courses/digital-design-verilog/module-09/09-03-assertions-sva/02-concurrent-assertions-and-temporal-logic/ Mon, 18 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-09/09-03-assertions-sva/02-concurrent-assertions-and-temporal-logic/ An immediate assertion checks one instant. A handshake’s real rule, request implies acknowledge within N cycles, spans time. Concurrent assertions are the one tool in this course built to express that kind of multi-cycle relationship directly. https://circuit.quest/courses/digital-design-verilog/module-09/09-03-assertions-sva/03-writing-properties-and-sequences/ Mon, 18 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-09/09-03-assertions-sva/03-writing-properties-and-sequences/ The last article of Module 9: naming temporal patterns as reusable sequences and properties, so an assertion library becomes documentation a design review can read, and a checklist every future test inherits.