https://circuit.quest/courses/digital-design-verilog/module-08/ Recent content in Module 8: RTL Coding for Quality & Synthesis on Circuit Quest Hugo en-us Mon, 04 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-08/08-01-coding-guidelines/01-naming-conventions-and-file-organization/ Mon, 04 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-08/08-01-coding-guidelines/01-naming-conventions-and-file-organization/ None of this changes what the RTL does. All of it changes how fast someone else, including you in six months, can trust it. The naming and file conventions real design teams enforce, and the reasons behind each. https://circuit.quest/courses/digital-design-verilog/module-08/08-01-coding-guidelines/02-reset-strategy-consistency/ Mon, 04 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-08/08-01-coding-guidelines/02-reset-strategy-consistency/ Naming inconsistency costs review time. Reset inconsistency can cost silicon. Why every module in a project needs to agree on reset polarity, reset type and reset domain boundaries, and what happens when they do not. https://circuit.quest/courses/digital-design-verilog/module-08/08-01-coding-guidelines/03-avoiding-sim-synth-mismatches/ Mon, 04 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-08/08-01-coding-guidelines/03-avoiding-sim-synth-mismatches/ You have met every cause of sim/synth mismatch already, scattered across five modules. This article is the checklist: all of them in one place, and the single coding discipline that prevents every one. https://circuit.quest/courses/digital-design-verilog/module-08/08-02-synthesis-aware-coding/01-what-synthesis-does-with-your-rtl/ Mon, 04 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-08/08-02-synthesis-aware-coding/01-what-synthesis-does-with-your-rtl/ You have known since Module 5 that if-else builds priority and case builds parallel decode. This article goes one level down, into what the synthesis tool does with those structures once you have written them. https://circuit.quest/courses/digital-design-verilog/module-08/08-02-synthesis-aware-coding/02-resource-sharing-area-vs-timing/ Mon, 04 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-08/08-02-synthesis-aware-coding/02-resource-sharing-area-vs-timing/ Write two additions in mutually exclusive branches of an if-else and a synthesis tool may quietly build only one adder, shared between them. When that happens, why it is usually a win, and the one case where you need to stop it. https://circuit.quest/courses/digital-design-verilog/module-08/08-02-synthesis-aware-coding/03-guiding-the-tool-without-fighting-it/ Mon, 04 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-08/08-02-synthesis-aware-coding/03-guiding-the-tool-without-fighting-it/ The two previous articles showed what synthesis does with your RTL. This one is about the discipline that follows: describe intent clearly, constrain honestly, and stop trying to out-think the optimiser at the line level. https://circuit.quest/courses/digital-design-verilog/module-08/08-03-timing-and-sta/01-setup-hold-and-the-critical-path/ Mon, 04 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-08/08-03-timing-and-sta/01-setup-hold-and-the-critical-path/ You met setup and hold for a single flip-flop in Module 3. Static timing analysis is the same check applied automatically to every path in a design with millions of flip-flops, without running a single simulation vector. https://circuit.quest/courses/digital-design-verilog/module-08/08-03-timing-and-sta/02-writing-basic-sdc-constraints/ Mon, 04 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-08/08-03-timing-and-sta/02-writing-basic-sdc-constraints/ A synthesis tool has no idea what clock frequency you are targeting unless you tell it, in a standard file format called SDC. The three constraints that appear in nearly every project, and what happens when they are wrong. https://circuit.quest/courses/digital-design-verilog/module-08/08-03-timing-and-sta/03-how-synthesis-optimizes-for-timing/ Mon, 04 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-08/08-03-timing-and-sta/03-how-synthesis-optimizes-for-timing/ Section 8.2 said resource sharing trades area for timing. This article shows the mechanism under every one of those trades: the levers a synthesis tool pulls once an SDC constraint tells it a path is tight. https://circuit.quest/courses/digital-design-verilog/module-08/08-03-timing-and-sta/04-reading-a-timing-report/ Mon, 04 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-08/08-03-timing-and-sta/04-reading-a-timing-report/ Everything in Section 8.3 has been building to this: opening a real timing report and knowing which line to look at, what it says, and where in the RTL the fix belongs. https://circuit.quest/courses/digital-design-verilog/module-08/08-04-common-bugs-and-debugging/01-x-propagation-in-practice/ Mon, 04 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-08/08-04-common-bugs-and-debugging/01-x-propagation-in-practice/ You met X-propagation briefly in Module 6. Now it gets the full treatment: where X comes from, how it spreads, and the technique for chasing an X back to the register it started at. https://circuit.quest/courses/digital-design-verilog/module-08/08-04-common-bugs-and-debugging/02-unintended-latch-inference-revisited/ Mon, 04 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-08/08-04-common-bugs-and-debugging/02-unintended-latch-inference-revisited/ You know why an incomplete always block infers a latch; Section 5.2 covered the mechanism. This article is the practical side: how to find one that has already made it into a real design, before it becomes a lab bug. https://circuit.quest/courses/digital-design-verilog/module-08/08-04-common-bugs-and-debugging/03-reset-domain-problems/ Mon, 04 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-08/08-04-common-bugs-and-debugging/03-reset-domain-problems/ Two modules, each correct, each verified on its own. Wire them together and the design fails at power-up. Reset domain bugs are why, and they are nearly invisible until integration. https://circuit.quest/courses/digital-design-verilog/module-08/08-04-common-bugs-and-debugging/04-multi-driver-conflicts/ Mon, 04 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-08/08-04-common-bugs-and-debugging/04-multi-driver-conflicts/ A signal with two drivers is not ambiguous in simulation; the simulator has a precise rule for it. That precision is what makes the bug easy to miss: it can look like a correct value for a long time before it does not. https://circuit.quest/courses/digital-design-verilog/module-08/08-04-common-bugs-and-debugging/05-a-systematic-debugging-methodology/ Mon, 04 May 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-08/08-04-common-bugs-and-debugging/05-a-systematic-debugging-methodology/ Every technique in Section 8.4, and most of Module 6, belongs in one converging method. A repeatable sequence that turns ’the testbench says FAIL’ into a confirmed root cause, applied to a worked example.