https://circuit.quest/courses/digital-design-verilog/module-07/ Recent content in Module 7: Advanced RTL Design Techniques on Circuit Quest Hugo en-us Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-01-parameterized-modules/01-why-parameterize-everything/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-01-parameterized-modules/01-why-parameterize-everything/ You met parameter in Module 4. This article is about the discipline that makes a module reusable across projects instead of copy-pasted between them. https://circuit.quest/courses/digital-design-verilog/module-07/07-01-parameterized-modules/02-generate-if-and-generate-case/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-01-parameterized-modules/02-generate-if-and-generate-case/ generate for repeats a structure. generate if and generate case choose between different structures at elaboration time, based on a parameter, and the branch not taken never becomes hardware. https://circuit.quest/courses/digital-design-verilog/module-07/07-01-parameterized-modules/03-parameterized-memory-model/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-01-parameterized-modules/03-parameterized-memory-model/ One parameterized RAM model, built properly once, is going to sit inside the FIFO in Section 7.4, the SRAM controller later on, and a good number of the testbenches you write after this course. https://circuit.quest/courses/digital-design-verilog/module-07/07-01-parameterized-modules/04-parameterized-arithmetic-unit/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-01-parameterized-modules/04-parameterized-arithmetic-unit/ One worked example that pulls together parameter, localparam, $clog2 and generate into a single width-configurable ALU you could drop into a project. https://circuit.quest/courses/digital-design-verilog/module-07/07-02-arithmetic-circuits/01-signed-arithmetic-pitfalls/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-02-arithmetic-circuits/01-signed-arithmetic-pitfalls/ Adding the signed keyword to a wire looks harmless. It changes how comparisons, shifts and mixed expressions evaluate, and each of those changes is a bug waiting for the test case you did not write. https://circuit.quest/courses/digital-design-verilog/module-07/07-02-arithmetic-circuits/02-saturating-arithmetic/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-02-arithmetic-circuits/02-saturating-arithmetic/ Ordinary binary addition wraps silently on overflow. In audio, video and control paths a wraparound turns a loud sample into a click or a stable controller into an oscillating one. Saturating arithmetic clamps instead. https://circuit.quest/courses/digital-design-verilog/module-07/07-02-arithmetic-circuits/03-pipelining-an-adder/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-02-arithmetic-circuits/03-pipelining-an-adder/ You know the general pipelining idea from Module 5. This is the specific case that comes up constantly: a wide adder whose carry chain is too long for one clock period, split across two stages without losing the carry. https://circuit.quest/courses/digital-design-verilog/module-07/07-02-arithmetic-circuits/04-pipelining-a-multiplier/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-02-arithmetic-circuits/04-pipelining-a-multiplier/ A multiplier’s critical path is far longer than an adder’s, which makes it the block that gains most from pipelining. Here is how to cut one across stages at a boundary that actually shortens the path. https://circuit.quest/courses/digital-design-verilog/module-07/07-03-pipeline-design/01-throughput-vs-latency-revisited/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-03-pipeline-design/01-throughput-vs-latency-revisited/ We have pipelined an adder and a multiplier one at a time. This article steps back to the real question: how many stages, and where exactly to cut, once you are looking at a whole datapath instead of one operator. https://circuit.quest/courses/digital-design-verilog/module-07/07-03-pipeline-design/02-inserting-pipeline-stages/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-03-pipeline-design/02-inserting-pipeline-stages/ The previous article decided the stages on paper. This one is the mechanics: taking a working combinational block and cutting a register into it without silently changing its behaviour. https://circuit.quest/courses/digital-design-verilog/module-07/07-03-pipeline-design/03-stalls-and-bubbles/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-03-pipeline-design/03-stalls-and-bubbles/ Every pipeline so far assumed data can move every cycle. Real pipelines feed into things that are not always ready, and a pipeline with no way to pause corrupts data the first time that happens. https://circuit.quest/courses/digital-design-verilog/module-07/07-03-pipeline-design/04-pipelined-mac-unit-worked-example/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-03-pipeline-design/04-pipelined-mac-unit-worked-example/ Everything from Section 7.3 in one design: a pipelined MAC unit, the most repeated operation in every digital filter and neural network accelerator. https://circuit.quest/courses/digital-design-verilog/module-07/07-04-fifos/01-why-fifos-exist/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-04-fifos/01-why-fifos-exist/ A FIFO is not a data structure borrowed from software. It is the hardware answer to one of the most common problems in digital design: two things that produce and consume data at rates that do not quite match. https://circuit.quest/courses/digital-design-verilog/module-07/07-04-fifos/02-synchronous-fifo-full-empty/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-04-fifos/02-synchronous-fifo-full-empty/ Equal read and write pointers mean either completely empty or completely full, and the two look identical unless you add one extra bit. Here is the trick, and a complete synchronous FIFO built on the memory model from Section 7.1. https://circuit.quest/courses/digital-design-verilog/module-07/07-04-fifos/03-gray-code-pointers/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-04-fifos/03-gray-code-pointers/ Synchronizing a single bit across clock domains is a solved problem. Synchronizing a multi-bit pointer is not, unless adjacent values differ in exactly one bit. That is Gray code, and it is why asynchronous FIFOs are possible at all. https://circuit.quest/courses/digital-design-verilog/module-07/07-04-fifos/04-asynchronous-fifo-and-cdc/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-04-fifos/04-asynchronous-fifo-and-cdc/ The most common clock-domain-crossing structure in real chips. Two independent clocks, one shared memory, and Gray-coded pointers synchronized across the boundary in both directions. https://circuit.quest/courses/digital-design-verilog/module-07/07-04-fifos/05-fifo-worked-example-and-testbench/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-04-fifos/05-fifo-worked-example-and-testbench/ Testing a design with two independent clocks is different from anything in Module 6: there is no single clock edge to synchronize your checks to. Here is how to do it on the async FIFO from the previous article. https://circuit.quest/courses/digital-design-verilog/module-07/07-05-clock-domain-crossing/01-metastability-and-mtbf-recap/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-05-clock-domain-crossing/01-metastability-and-mtbf-recap/ Module 3 showed that metastability exists and cannot be eliminated. This article gives the formula design teams use to decide whether a synchronizer is safe enough to ship, and what changes that number. https://circuit.quest/courses/digital-design-verilog/module-07/07-05-clock-domain-crossing/02-two-flop-synchronizer/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-05-clock-domain-crossing/02-two-flop-synchronizer/ We have built a two-flop synchronizer twice already, once for reset in Module 5 and once for FIFO pointers in this module. Time to build it once, properly, with the synthesis attribute it needs. https://circuit.quest/courses/digital-design-verilog/module-07/07-05-clock-domain-crossing/03-multi-bit-cdc-and-handshake/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-05-clock-domain-crossing/03-multi-bit-cdc-and-handshake/ Gray code solves multi-bit CDC for values that only ever increment. For an arbitrary data word that jumps around, you need the request/acknowledge handshake. https://circuit.quest/courses/digital-design-verilog/module-07/07-05-clock-domain-crossing/04-cdc-lint-and-common-mistakes/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-05-clock-domain-crossing/04-cdc-lint-and-common-mistakes/ Metastability does not exist in RTL simulation. A simulator resolves every signal to a clean 0 or 1, instantly. So every CDC bug in this section is invisible to the tool you would normally trust to find bugs. https://circuit.quest/courses/digital-design-verilog/module-07/07-06-low-power-design/01-clock-gating-in-rtl/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-06-low-power-design/01-clock-gating-in-rtl/ You already know never to gate a clock with a bare AND gate. This article explains what a real integrated clock gating cell does differently: a latch, not a gate, and one specific reason the latch has to be there. https://circuit.quest/courses/digital-design-verilog/module-07/07-06-low-power-design/02-power-gating-overview/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-06-low-power-design/02-power-gating-overview/ Clock gating stops a block from switching. Power gating disconnects it from the supply, which removes the leakage that clock gating cannot touch, and brings a set of problems clock gating never had. https://circuit.quest/courses/digital-design-verilog/module-07/07-06-low-power-design/03-operand-isolation/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-06-low-power-design/03-operand-isolation/ A multiplier whose result nobody will use is still burning power on every switching input, this cycle. Operand isolation is the small, RTL-visible fix, and unlike the last two techniques it is something you can write yourself. https://circuit.quest/courses/digital-design-verilog/module-07/07-06-low-power-design/04-activity-aware-design-principles/ Mon, 20 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-07/07-06-low-power-design/04-activity-aware-design-principles/ Three power techniques, three different problems. This closing article is the decision framework that ties clock gating, power gating and operand isolation together, and a look back over Module 7.