https://circuit.quest/courses/digital-design-verilog/module-06/ Recent content in Module 6: Verilog for Testbench & Simulation on Circuit Quest Hugo en-us Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-01-testbench-architecture/01-why-testbenches-exist/ Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-01-testbench-architecture/01-why-testbenches-exist/ Synthesis passing is not the design working. What the simulator does, why hardware cannot be debugged like software, a first testbench, and the assumption every verification effort starts from. https://circuit.quest/courses/digital-design-verilog/module-06/06-01-testbench-architecture/02-anatomy-of-a-testbench/ Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-01-testbench-architecture/02-anatomy-of-a-testbench/ Instance, stimulus, checker, report. Why the testbench has no ports, which side gets reg and which gets wire, and a skeleton to build on. https://circuit.quest/courses/digital-design-verilog/module-06/06-01-testbench-architecture/03-driving-the-dut/ Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-01-testbench-architecture/03-driving-the-dut/ Exhaustive loops for combinational inputs, the drive-after-the-edge rule for clocked ones, why driving on the edge is a race, and tasks for stimulus that repeats. https://circuit.quest/courses/digital-design-verilog/module-06/06-01-testbench-architecture/04-observing-and-sampling-outputs/ Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-01-testbench-architecture/04-observing-and-sampling-outputs/ Why reading a registered output at the clock edge gives last cycle’s value, the two safe ways to sample, and $strobe against $display with a trace. https://circuit.quest/courses/digital-design-verilog/module-06/06-01-testbench-architecture/05-the-self-checking-loop/ Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-01-testbench-architecture/05-the-self-checking-loop/ An error counter, a comparison with !==, a final verdict, and a check task: the 4-bit adder tested over all 512 input combinations without anyone reading a number. https://circuit.quest/courses/digital-design-verilog/module-06/06-02-simulation-only-constructs/01-display-monitor-and-strobe/ Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-02-simulation-only-constructs/01-display-monitor-and-strobe/ Three ways to print, firing at three different points in the time step, with the format specifiers, $timeformat, $write, and a trace that shows all three side by side. https://circuit.quest/courses/digital-design-verilog/module-06/06-02-simulation-only-constructs/02-simulation-control-tasks/ Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-02-simulation-only-constructs/02-simulation-control-tasks/ Ending a simulation, reading the time, the watchdog that kills a hung run, and the four severity tasks that report failures with a grade. https://circuit.quest/courses/digital-design-verilog/module-06/06-02-simulation-only-constructs/03-file-io-in-verilog/ Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-02-simulation-only-constructs/03-file-io-in-verilog/ $fopen, $fdisplay and $fclose; the multichannel descriptor that writes to a file and the console with one call; reading with $fscanf; and a testbench that logs every vector. https://circuit.quest/courses/digital-design-verilog/module-06/06-02-simulation-only-constructs/04-readmemh-and-readmemb/ Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-02-simulation-only-constructs/04-readmemh-and-readmemb/ Test vectors as data in a text file rather than literals in the testbench: the file format, loading into an array, address ranges, packed records, and an ALU testbench driven from a file. https://circuit.quest/courses/digital-design-verilog/module-06/06-02-simulation-only-constructs/05-timing-control-constructs/ Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-02-simulation-only-constructs/05-timing-control-constructs/ The three ways a testbench yields and waits: a fixed delay, an edge, or a condition. When each is right, why wait() catches a signal that is already high, and a reset-and-handshake sequence using all three. https://circuit.quest/courses/digital-design-verilog/module-06/06-03-clocks-and-resets/01-generating-clocks/ Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-03-clocks-and-resets/01-generating-clocks/ The three-line clock, why the reg must be initialised, the forever form, duty cycles other than 50 percent, several clocks, and phase offsets. https://circuit.quest/courses/digital-design-verilog/module-06/06-03-clocks-and-resets/02-reset-assertion-protocols/ Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-03-clocks-and-resets/02-reset-assertion-protocols/ How long to hold reset, why to release it a little after a clock edge whether the design’s reset is synchronous or not, the active-low convention, and a template. https://circuit.quest/courses/digital-design-verilog/module-06/06-03-clocks-and-resets/03-initialization-sequences/ Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-03-clocks-and-resets/03-initialization-sequences/ How one undriven input turns a whole design to x, the start-up order that prevents it, inline against procedural initial values, driving x on purpose, and what x looks like in a printout. https://circuit.quest/courses/digital-design-verilog/module-06/06-03-clocks-and-resets/04-multi-clock-testbenches/ Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-03-clocks-and-resets/04-multi-clock-testbenches/ Two independent clocks, the rule that each signal is driven from the clock of the domain it feeds, resets in parallel with fork and join, and crossing domains with a handshake rather than a delay. https://circuit.quest/courses/digital-design-verilog/module-06/06-04-self-checking-tests/01-the-pass-fail-mindset/ Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-04-self-checking-tests/01-the-pass-fail-mindset/ The arithmetic of input spaces, what regression testing means, what a bug costs at each stage, and the same adder tested by eye and by code. https://circuit.quest/courses/digital-design-verilog/module-06/06-04-self-checking-tests/02-immediate-assertions-and-error-tasks/ Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-04-self-checking-tests/02-immediate-assertions-and-error-tasks/ The four severity tasks and when each fits, the immediate assertion form, what a useful error message contains, and a check task that uses all of them. https://circuit.quest/courses/digital-design-verilog/module-06/06-04-self-checking-tests/03-golden-reference-models/ Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-04-self-checking-tests/03-golden-reference-models/ A second, obviously correct implementation beside the design, computing the expected value for any input: a multiplier, a CRC, and a stateful counter model. https://circuit.quest/courses/digital-design-verilog/module-06/06-04-self-checking-tests/04-comparing-dut-vs-reference/ Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-04-self-checking-tests/04-comparing-dut-vs-reference/ Why == lets an x pass and === does not, a reusable check task, an exhaustive loop for 8-bit inputs, and a corner-value set for 32-bit ones. https://circuit.quest/courses/digital-design-verilog/module-06/06-04-self-checking-tests/05-directed-tests-and-test-vectors/ Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-04-self-checking-tests/05-directed-tests-and-test-vectors/ The inputs most likely to fail, named test cases so that a failure says what broke, a directed suite followed by a sweep, and the tiers a test suite falls into. https://circuit.quest/courses/digital-design-verilog/module-06/06-05-waveform-analysis/01-value-change-dump/ Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-05-waveform-analysis/01-value-change-dump/ The two-line dump, what the depth and scope arguments do, keeping the file small, windowed recording, what the file looks like inside, and the FST alternative. https://circuit.quest/courses/digital-design-verilog/module-06/06-05-waveform-analysis/02-navigating-gtkwave/ Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-05-waveform-analysis/02-navigating-gtkwave/ Opening a file, adding signals, zooming, the two cursors and what they measure, groups and aliases, radix, and the save file that keeps your layout. https://circuit.quest/courses/digital-design-verilog/module-06/06-05-waveform-analysis/03-reading-waveforms-like-a-pro/ Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-05-waveform-analysis/03-reading-waveforms-like-a-pro/ Work from the wrong output backwards; then the shapes to recognise: x propagation, glitches, setup and hold signatures, state decoding with a translate file, and pipeline latency. https://circuit.quest/courses/digital-design-verilog/module-06/06-05-waveform-analysis/04-from-waveform-to-bug-fix/ Sun, 05 Apr 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-06/06-05-waveform-analysis/04-from-waveform-to-bug-fix/ One bug the whole way: the error message, checking the inputs, tracing the datapath, a specific hypothesis, the fix, the re-run and the regression, with an off-by-one counter as the example.