https://circuit.quest/courses/digital-design-verilog/module-05/ Recent content in Module 5: Behavioral Verilog for Synthesis on Circuit Quest Hugo en-us Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-01-procedural-blocks/01-the-concurrent-world-of-verilog/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-01-procedural-blocks/01-the-concurrent-world-of-verilog/ always blocks, assigns and instances are all active at once; how the event-driven simulator models that; and the two places where the order the simulator picks can change the answer. https://circuit.quest/courses/digital-design-verilog/module-05/05-01-procedural-blocks/02-always-vs-initial/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-01-procedural-blocks/02-always-vs-initial/ always runs forever and is hardware; initial runs once at time zero and is not. The three forms of always, what initial is for, and why using it to initialise a register fails in silicon. https://circuit.quest/courses/digital-design-verilog/module-05/05-01-procedural-blocks/03-blocking-assignments/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-01-procedural-blocks/03-blocking-assignments/ What blocking means, why sequential steps inside a combinational block still produce combinational logic, a mux and a priority encoder done right, and the race that = creates in a clocked block. https://circuit.quest/courses/digital-design-verilog/module-05/05-01-procedural-blocks/04-nonblocking-assignments/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-01-procedural-blocks/04-nonblocking-assignments/ The two-phase time step: every right-hand side is read, then every left-hand side is updated. Why that makes flip-flop models correct whatever order the blocks run in, shown on a swap and a pipeline. https://circuit.quest/courses/digital-design-verilog/module-05/05-01-procedural-blocks/05-the-nba-scheduling-model/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-01-procedural-blocks/05-the-nba-scheduling-model/ The stratified event queue: active, non-blocking and postponed regions, delta cycles, a clock edge traced with and without the race, and why $display lies where $strobe does not. https://circuit.quest/courses/digital-design-verilog/module-05/05-02-sensitivity-lists/01-what-is-a-sensitivity-list/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-02-sensitivity-lists/01-what-is-a-sensitivity-list/ What the @(…) means, level against edge sensitivity, and how that choice decides whether the block becomes gates, a flip-flop or a latch. https://circuit.quest/courses/digital-design-verilog/module-05/05-02-sensitivity-lists/02-always-star-construct/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-02-sensitivity-lists/02-always-star-construct/ The automatic sensitivity list: what it includes, what it leaves out, converting old code to it, and the SystemVerilog always_comb that goes one step further. https://circuit.quest/courses/digital-design-verilog/module-05/05-02-sensitivity-lists/03-incomplete-sensitivity-lists/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-02-sensitivity-lists/03-incomplete-sensitivity-lists/ A missing signal traced event by event: the simulation models storage the synthesiser will not build, the tests pass, and the silicon is different. How to see it and the one fix. https://circuit.quest/courses/digital-design-verilog/module-05/05-02-sensitivity-lists/04-latch-inference-and-avoidance/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-02-sensitivity-lists/04-latch-inference-and-avoidance/ The two shapes of code that make the synthesiser build a latch, the default-assignment habit that rules them out, what the warnings look like, and the few places a latch is meant. https://circuit.quest/courses/digital-design-verilog/module-05/05-03-conditional-and-case/01-if-else-in-always-blocks/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-03-conditional-and-case/01-if-else-in-always-blocks/ An if-else chain is a chain of muxes with the first condition winning. When that priority is what the specification wants, what it costs in depth, and why an if without else is a latch in one kind of block and an enable in the other. https://circuit.quest/courses/digital-design-verilog/module-05/05-03-conditional-and-case/02-case-statement/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-03-conditional-and-case/02-case-statement/ case compares one expression against a list of values. With distinct constant values it builds a flat decoder rather than a chain; it needs a default for the same reason if needs an else; and it is the natural way to decode a state. https://circuit.quest/courses/digital-design-verilog/module-05/05-03-conditional-and-case/03-casex-and-casez/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-03-conditional-and-case/03-casex-and-casez/ Both add don’t-care bits to case items. casez treats ? and z as wildcards; casex also treats x as one, which hides unknowns in simulation and gives silicon that behaves differently. Use casez. https://circuit.quest/courses/digital-design-verilog/module-05/05-03-conditional-and-case/04-full-case-and-parallel-case/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-03-conditional-and-case/04-full-case-and-parallel-case/ Two synthesis pragmas that promise the tool a case is complete or its arms exclusive, the mismatch you get when the promise is false, and the SystemVerilog keywords that replace them. https://circuit.quest/courses/digital-design-verilog/module-05/05-03-conditional-and-case/05-priority-vs-parallel-decode/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-03-conditional-and-case/05-priority-vs-parallel-decode/ Choosing between a priority chain and a flat decoder on purpose: what each costs, which specifications need priority, the accidental-priority bug, and a parameterised encoder with an exhaustive test. https://circuit.quest/courses/digital-design-verilog/module-05/05-04-loops/01-for-loops-and-synthesis/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-04-loops/01-for-loops-and-synthesis/ A for loop in RTL is unrolled into parallel hardware when the design is built, not run when it operates. What that requires of the loop, and a parity generator and a popcount that scale with a parameter. https://circuit.quest/courses/digital-design-verilog/module-05/05-04-loops/02-while-repeat-and-forever/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-04-loops/02-while-repeat-and-forever/ The other three loops, which ones synthesise, and what each is for in a testbench: waiting a number of cycles, waiting for a condition, and generating a clock. https://circuit.quest/courses/digital-design-verilog/module-05/05-04-loops/03-loops-for-hardware-patterns/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-04-loops/03-loops-for-hardware-patterns/ Four circuits built with a parameterised for loop: a Gray code encoder, a leading-zero counter, a bit reversal that costs no gates, and an equality comparator, with a self-checking testbench. https://circuit.quest/courses/digital-design-verilog/module-05/05-04-loops/04-generate-for-vs-procedural-loops/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-04-loops/04-generate-for-vs-procedural-loops/ Two loops with one keyword: a procedural for unrolls an expression inside a block, a generate for stamps out instances, wires and assigns at module level. Which does what, and the label that makes generated instances addressable. https://circuit.quest/courses/digital-design-verilog/module-05/05-05-flip-flops-and-registers/01-inferring-d-flip-flops/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-05-flip-flops-and-registers/01-inferring-d-flip-flops/ Three lines that become a physical flip-flop, why the edge in the sensitivity list is what does it, several registers in one block, the logic between the edges, and checking the result in Yosys. https://circuit.quest/courses/digital-design-verilog/module-05/05-05-flip-flops-and-registers/02-synchronous-vs-asynchronous-reset/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-05-flip-flops-and-registers/02-synchronous-vs-asynchronous-reset/ Synchronous and asynchronous reset in Verilog, what each costs, the release-timing problem of the asynchronous kind, and the two-flop synchroniser that asserts asynchronously and releases synchronously. https://circuit.quest/courses/digital-design-verilog/module-05/05-05-flip-flops-and-registers/03-clock-enable-and-load-signals/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-05-flip-flops-and-registers/03-clock-enable-and-load-signals/ The enable pattern that maps onto a flip-flop’s clock-enable pin, the priority between reset, clear and enable, and why gating a clock with an AND gate in RTL is the one thing not to do. https://circuit.quest/courses/digital-design-verilog/module-05/05-05-flip-flops-and-registers/04-register-design-patterns/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-05-flip-flops-and-registers/04-register-design-patterns/ Six register shapes that recur in every design, up counter, up/down counter, modulo-N counter, serial-in and parallel-in shift registers, and a saturating accumulator, all the same enable-and-reset structure with a different next value. https://circuit.quest/courses/digital-design-verilog/module-05/05-05-flip-flops-and-registers/05-pipeline-registers-and-valid-signals/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-05-flip-flops-and-registers/05-pipeline-registers-and-valid-signals/ Cutting a long combinational path into stages with registers between them: what it buys in clock rate, what it costs in latency, and the valid bit that travels with the data. https://circuit.quest/courses/digital-design-verilog/module-05/05-06-modeling-fsms/01-fsm-anatomy-in-rtl/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-06-modeling-fsms/01-fsm-anatomy-in-rtl/ The state register, the next-state logic and the output logic of section 3.3, each as an always block; state encodings with localparam; and where Moore and Mealy differ in the code. https://circuit.quest/courses/digital-design-verilog/module-05/05-06-modeling-fsms/02-one-process-fsm-style/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-06-modeling-fsms/02-one-process-fsm-style/ State, next state and outputs in one clocked block: the shortest state machine, with every output registered, which is either exactly right or a one-cycle surprise depending on what the outputs are for. https://circuit.quest/courses/digital-design-verilog/module-05/05-06-modeling-fsms/03-two-process-fsm-style/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-06-modeling-fsms/03-two-process-fsm-style/ The state register in a clocked block, next state and outputs in a combinational one: the style in every vendor’s guide, and how Moore and Mealy outputs fit the same template. https://circuit.quest/courses/digital-design-verilog/module-05/05-06-modeling-fsms/04-three-process-fsm-style/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-06-modeling-fsms/04-three-process-fsm-style/ State register, next-state logic and output logic in three blocks: each answers one question, at the cost of one more block to keep in step. A comparison of the three styles. https://circuit.quest/courses/digital-design-verilog/module-05/05-06-modeling-fsms/05-state-encoding-and-safe-fsm/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-06-modeling-fsms/05-state-encoding-and-safe-fsm/ Five states in three bits leave three encodings that mean nothing. How a machine gets into one, why it might never leave, and the one line that guarantees recovery. https://circuit.quest/courses/digital-design-verilog/module-05/05-06-modeling-fsms/06-fsm-worked-examples/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-05/05-06-modeling-fsms/06-fsm-worked-examples/ The three machines designed by hand in Module 3, now as tested RTL: a Moore traffic light with a timer, a Mealy sequence detector that handles overlap, and a vending machine split into a controller and a datapath. Then a look back over Module 5.