https://circuit.quest/courses/digital-design-verilog/module-04/ Recent content in Module 4: Introduction to Verilog HDL on Circuit Quest Hugo en-us Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-01-why-hdl/01-the-hardware-description-revolution/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-01-why-hdl/01-the-hardware-description-revolution/ Why hand-drawn design stopped scaling, what a hardware description language actually buys you, and where Verilog came from. https://circuit.quest/courses/digital-design-verilog/module-04/04-01-why-hdl/02-simulation-vs-synthesis/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-01-why-hdl/02-simulation-vs-synthesis/ The same Verilog file is read by a simulator and a synthesiser with different rules. The RTL subset is what both agree on, and a design file must stay inside it. https://circuit.quest/courses/digital-design-verilog/module-04/04-01-why-hdl/03-the-design-and-verification-flow/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-01-why-hdl/03-the-design-and-verification-flow/ The ten steps between a specification and a finished chip, what each one costs when it finds a bug, and which of them this course covers. https://circuit.quest/courses/digital-design-verilog/module-04/04-01-why-hdl/04-verilog-vs-vhdl-vs-systemverilog/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-01-why-hdl/04-verilog-vs-vhdl-vs-systemverilog/ The three languages you will meet, the same flip-flop written in each, and why this course teaches Verilog-2001. https://circuit.quest/courses/digital-design-verilog/module-04/04-01-why-hdl/05-thinking-in-hardware/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-01-why-hdl/05-thinking-in-hardware/ Five habits from software that produce broken Verilog, and the picture to replace them with: every line is a piece of a circuit. https://circuit.quest/courses/digital-design-verilog/module-04/04-02-verilog-basics/01-modules-and-ports/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-02-verilog-basics/01-modules-and-ports/ The module is the unit of every Verilog design. Its declaration, its port directions, the ANSI style the course uses, and the older style you will meet in other people’s code. https://circuit.quest/courses/digital-design-verilog/module-04/04-02-verilog-basics/02-wire-and-reg-data-types/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-02-verilog-basics/02-wire-and-reg-data-types/ reg does not mean register. What the two keywords actually mean, the one rule that decides which to use, and what really determines whether you get a flip-flop. https://circuit.quest/courses/digital-design-verilog/module-04/04-02-verilog-basics/03-vectors-and-arrays/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-02-verilog-basics/03-vectors-and-arrays/ Multi-bit signals: declaring vectors, selecting bits and fields, concatenating and replicating, and modelling memories as arrays. https://circuit.quest/courses/digital-design-verilog/module-04/04-02-verilog-basics/04-parameters-and-localparams/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-02-verilog-basics/04-parameters-and-localparams/ Write a module once and instantiate it at any width: parameters, localparams for internal constants, and $clog2 for derived widths. https://circuit.quest/courses/digital-design-verilog/module-04/04-02-verilog-basics/05-number-literals/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-02-verilog-basics/05-number-literals/ How to write a constant so that its width is what you meant, why unsized literals cause silent bugs, and what x and z are for. https://circuit.quest/courses/digital-design-verilog/module-04/04-02-verilog-basics/06-compiler-directives/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-02-verilog-basics/06-compiler-directives/ timescale, define and ifdef, include, and default_nettype none, the two-line directive that catches misspelt signal names at compile time. https://circuit.quest/courses/digital-design-verilog/module-04/04-02-verilog-basics/07-verilog-style-and-conventions/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-02-verilog-basics/07-verilog-style-and-conventions/ Naming, reset conventions, one register per always block, layout and comments: the RTL style rules that exist because each one prevents a particular bug. https://circuit.quest/courses/digital-design-verilog/module-04/04-03-operators/01-arithmetic-operators/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-03-operators/01-arithmetic-operators/ Add, subtract, multiply, and what each one costs in gates; the width rules that decide whether a carry is kept or lost; why division stays out of RTL; and signed arithmetic. https://circuit.quest/courses/digital-design-verilog/module-04/04-03-operators/02-relational-and-logical-operators/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-03-operators/02-relational-and-logical-operators/ Comparisons and the comparators they build, the case-equality operators that only exist in simulation, and why a && b and a & b are different circuits. https://circuit.quest/courses/digital-design-verilog/module-04/04-03-operators/03-bitwise-and-reduction-operators/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-03-operators/03-bitwise-and-reduction-operators/ Bitwise operators for masking, setting, clearing and toggling; reduction operators for zero detection, all-ones and parity; and the gates behind each. https://circuit.quest/courses/digital-design-verilog/module-04/04-03-operators/04-shift-and-concatenation-operators/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-03-operators/04-shift-and-concatenation-operators/ Logical and arithmetic shifts, the barrel shifter a variable shift becomes, and concatenation and replication for packing, unpacking and sign extension. https://circuit.quest/courses/digital-design-verilog/module-04/04-03-operators/05-conditional-operator/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-03-operators/05-conditional-operator/ sel ? a : b is a 2-to-1 multiplexer. Conditions, chains that become priority logic, and when to stop chaining and write a case statement. https://circuit.quest/courses/digital-design-verilog/module-04/04-03-operators/06-operator-precedence-and-pitfalls/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-03-operators/06-operator-precedence-and-pitfalls/ The precedence table, the four traps in it that produce silent bugs, the width rules for expressions that are not plain assignments, and the habit that avoids all of it. https://circuit.quest/courses/digital-design-verilog/module-04/04-04-structural-modeling/01-gate-primitives/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-04-structural-modeling/01-gate-primitives/ The built-in gates, output first and inputs after; buffers and tri-state drivers; an SR latch and a full adder built from them; and why you will read them far more often than write them. https://circuit.quest/courses/digital-design-verilog/module-04/04-04-structural-modeling/02-module-instantiation/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-04-structural-modeling/02-module-instantiation/ Placing a verified module inside another: the syntax, named against positional connection, parameters at instantiation, literals on ports, and what to do with ports you do not use. https://circuit.quest/courses/digital-design-verilog/module-04/04-04-structural-modeling/03-port-connection-styles/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-04-structural-modeling/03-port-connection-styles/ What happens when a signal and a port differ in width, how to spread a bus across instances with part-selects, tying ports off, and the one-driver rule. https://circuit.quest/courses/digital-design-verilog/module-04/04-04-structural-modeling/04-hierarchical-design/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-04-structural-modeling/04-hierarchical-design/ Why designs are trees of modules, a 4-bit adder from four full adders, the same adder at any width with a generate loop, and hierarchical names for probing inside instances. https://circuit.quest/courses/digital-design-verilog/module-04/04-04-structural-modeling/05-structural-modeling-worked-example/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-04-structural-modeling/05-structural-modeling-worked-example/ Half adder, full adder, adder-subtractor, logic unit and ALU, each built from the one below, with a testbench and a trace of one addition through every level. https://circuit.quest/courses/digital-design-verilog/module-04/04-05-dataflow-modeling/01-continuous-assignments/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-05-dataflow-modeling/01-continuous-assignments/ The assign statement: a piece of logic that always exists, evaluated in parallel with every other, driving one wire. Its rules, and when to use it over an always block. https://circuit.quest/courses/digital-design-verilog/module-04/04-05-dataflow-modeling/02-dataflow-operators-in-practice/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-05-dataflow-modeling/02-dataflow-operators-in-practice/ The common circuits of RTL as assign statements, from gates and reductions through comparators, muxes and shifters, to a parameterised ALU with flags. https://circuit.quest/courses/digital-design-verilog/module-04/04-05-dataflow-modeling/03-conditional-dataflow/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-05-dataflow-modeling/03-conditional-dataflow/ The three selection blocks of section 1.5 in dataflow style, and a BCD to seven-segment decoder with a self-checking testbench. https://circuit.quest/courses/digital-design-verilog/module-04/04-05-dataflow-modeling/04-dataflow-modeling-worked-example/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-05-dataflow-modeling/04-dataflow-modeling-worked-example/ Specification, architecture, RTL, a directed testbench with tasks, a random testbench with a reference model, waveforms, and what synthesis produces, for an N-bit signed-or-unsigned comparator. https://circuit.quest/courses/digital-design-verilog/module-04/04-05-dataflow-modeling/05-choosing-your-modeling-style/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-04/04-05-dataflow-modeling/05-choosing-your-modeling-style/ When to instantiate, when to assign, and when an always block is the only option; how the three coexist in one module; and a look back over Module 4.