https://circuit.quest/courses/digital-design-verilog/module-03/ Recent content in Module 3: Sequential Circuit Design on Circuit Quest Hugo en-us Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-01-latches-flip-flops/01-the-memory-problem/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-01-latches-flip-flops/01-the-memory-problem/ Why combinational circuits cannot remember, and how one feedback connection gives a circuit two stable states and therefore one bit of memory. https://circuit.quest/courses/digital-design-verilog/module-03/03-01-latches-flip-flops/02-sr-latch/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-01-latches-flip-flops/02-sr-latch/ Two NAND gates with their outputs crossed: set, reset, hold, and the forbidden state, with a switch debouncer as the application. https://circuit.quest/courses/digital-design-verilog/module-03/03-01-latches-flip-flops/03-d-latch/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-01-latches-flip-flops/03-d-latch/ One data input and an enable: the D latch removes the forbidden state, but its transparency causes a timing problem that leads to the flip-flop. https://circuit.quest/courses/digital-design-verilog/module-03/03-01-latches-flip-flops/04-d-flip-flop/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-01-latches-flip-flops/04-d-flip-flop/ Two D latches with opposite enables make an edge-triggered flip-flop, the element every synchronous design is built from. Also: synchronous and asynchronous reset, and the enable input. https://circuit.quest/courses/digital-design-verilog/module-03/03-01-latches-flip-flops/05-jk-t-flip-flops/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-01-latches-flip-flops/05-jk-t-flip-flops/ The JK and T flip-flops, their characteristic equations, how to build them from a D flip-flop, and the excitation tables that make counter and state machine design systematic. https://circuit.quest/courses/digital-design-verilog/module-03/03-01-latches-flip-flops/06-timing-parameters/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-01-latches-flip-flops/06-timing-parameters/ The four timing parameters of a flip-flop, the two constraint equations they give, maximum clock frequency, and why timing has to be met at every process, voltage and temperature corner. https://circuit.quest/courses/digital-design-verilog/module-03/03-02-synchronous-asynchronous/01-two-worlds-of-sequential-design/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-02-synchronous-asynchronous/01-two-worlds-of-sequential-design/ The two ways a sequential circuit can decide when to change state, why the industry settled on the clocked one, and the contract a synchronous design has to keep. https://circuit.quest/courses/digital-design-verilog/module-03/03-02-synchronous-asynchronous/02-clock-signals-and-distribution/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-02-synchronous-asynchronous/02-clock-signals-and-distribution/ What makes a good clock, how it is generated from a crystal and a PLL, and how a clock tree delivers it to millions of flip-flops with only a few tens of picoseconds of skew. https://circuit.quest/courses/digital-design-verilog/module-03/03-02-synchronous-asynchronous/03-synchronous-design-discipline/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-02-synchronous-asynchronous/03-synchronous-design-discipline/ Six rules that keep a design analysable, and the specific failure each one prevents: state in flip-flops, no combinational loops, synchronised inputs, managed resets, proper clock gating. https://circuit.quest/courses/digital-design-verilog/module-03/03-02-synchronous-asynchronous/04-dangers-of-asynchronous-design/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-02-synchronous-asynchronous/04-dangers-of-asynchronous-design/ Critical races, essential hazards and the reset release problem: the failures that appear when state changes are not serialised by a clock. https://circuit.quest/courses/digital-design-verilog/module-03/03-02-synchronous-asynchronous/05-metastability/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-02-synchronous-asynchronous/05-metastability/ Every flip-flop can get stuck between 0 and 1. It cannot be prevented, only made rare: the physics, the MTBF calculation, and the synchroniser. https://circuit.quest/courses/digital-design-verilog/module-03/03-03-finite-state-machines/01-what-is-a-state-machine/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-03-finite-state-machines/01-what-is-a-state-machine/ The formal definition of a finite state machine, the hardware it maps onto, and where you meet them, from traffic lights to the control unit of a processor. https://circuit.quest/courses/digital-design-verilog/module-03/03-03-finite-state-machines/02-mealy-vs-moore/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-03-finite-state-machines/02-mealy-vs-moore/ The single structural difference between Moore and Mealy machines, and what it does to state count, output timing and glitches. https://circuit.quest/courses/digital-design-verilog/module-03/03-03-finite-state-machines/03-state-diagrams-tables/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-03-finite-state-machines/03-state-diagrams-tables/ The two notations for a state machine, the conventions for drawing one, a sequence detector worked out state by state, and the mistakes to look for. https://circuit.quest/courses/digital-design-verilog/module-03/03-03-finite-state-machines/04-state-encoding/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-03-finite-state-machines/04-state-encoding/ Binary, one-hot, Gray and output-coded state assignments, what each does to area and speed, and why FPGA tools default to one-hot. https://circuit.quest/courses/digital-design-verilog/module-03/03-03-finite-state-machines/05-fsm-design-flow/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-03-finite-state-machines/05-fsm-design-flow/ Eight steps from a written specification to a gate-level state machine, with a small example carried all the way through and state minimisation by the implication table. https://circuit.quest/courses/digital-design-verilog/module-03/03-03-finite-state-machines/06-fsm-worked-example-traffic-light/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-03-finite-state-machines/06-fsm-worked-example-traffic-light/ The eight-step flow applied to a traffic light with a pedestrian request, from specification to next-state equations and a simulated cycle. https://circuit.quest/courses/digital-design-verilog/module-03/03-03-finite-state-machines/07-fsm-worked-example-serial-detector/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-03-finite-state-machines/07-fsm-worked-example-serial-detector/ A detector for the bit sequence 1011 in a serial stream, with overlapping matches, worked through to equations, plus the Mealy version and a simulation. https://circuit.quest/courses/digital-design-verilog/module-03/03-03-finite-state-machines/08-fsm-worked-example-vending-machine/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-03-finite-state-machines/08-fsm-worked-example-vending-machine/ A vending machine done as a pure state machine and then as a small state machine with a datapath, to show where one approach stops scaling and the other begins. https://circuit.quest/courses/digital-design-verilog/module-03/03-04-registers-shift-registers/01-registers-parallel-load/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-04-registers-shift-registers/01-registers-parallel-load/ N flip-flops on one clock make a register. Adding enable, clear and load turns it into the block that every datapath is made of. https://circuit.quest/courses/digital-design-verilog/module-03/03-04-registers-shift-registers/02-shift-register-types/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-04-registers-shift-registers/02-shift-register-types/ A chain of flip-flops that moves data one place per clock, in its four forms, and how they turn a serial wire into a byte and back. https://circuit.quest/courses/digital-design-verilog/module-03/03-04-registers-shift-registers/03-shift-register-applications/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-04-registers-shift-registers/03-shift-register-applications/ Five things a chain of flip-flops does in real designs: delay lines, UART frames, ring counters, linear-feedback sequences and CRCs, and the scan chains used to test chips. https://circuit.quest/courses/digital-design-verilog/module-03/03-04-registers-shift-registers/04-universal-shift-register/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-04-registers-shift-registers/04-universal-shift-register/ Hold, shift right, shift left and parallel load in one register with a two-bit mode input: the design, the 74HC194 that implements it, and how to cascade them. https://circuit.quest/courses/digital-design-verilog/module-03/03-05-counters/01-ripple-counters/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-05-counters/01-ripple-counters/ The cheapest counter there is, a chain of toggle flip-flops, and the timing problem that makes it unsuitable for most of what counters are used for. https://circuit.quest/courses/digital-design-verilog/module-03/03-05-counters/02-synchronous-counters/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-05-counters/02-synchronous-counters/ Clock every flip-flop from the same clock and compute the toggles in advance. Enable, clear, load, terminal count for cascading, and the fact that a counter is an adder. https://circuit.quest/courses/digital-design-verilog/module-03/03-05-counters/03-modulo-n-counters/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-05-counters/03-modulo-n-counters/ Counting to 6, 10, 12 or 60 with a binary counter: synchronous clear on N-1, preload, or a custom state machine, and why decoding N with an asynchronous reset is a mistake. https://circuit.quest/courses/digital-design-verilog/module-03/03-05-counters/04-up-down-and-special-counters/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-05-counters/04-up-down-and-special-counters/ Four counters for specific jobs: up/down for bidirectional counting, Gray code for pointers that cross clock domains, Johnson for cheap decoding and phase generation, ring for one-hot sequencing. https://circuit.quest/courses/digital-design-verilog/module-03/03-05-counters/05-counter-applications/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-05-counters/05-counter-applications/ Five things counters do in real designs: divide a clock, generate PWM, run a stopwatch, walk through memory addresses, and time the bits of a UART. https://circuit.quest/courses/digital-design-verilog/module-03/03-06-memory-elements/01-register-files/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-06-memory-elements/01-register-files/ Thirty-two registers, two reads and a write every cycle: a decoder on the write side, a mux per read port, and what happens when the same register is read and written at once. https://circuit.quest/courses/digital-design-verilog/module-03/03-06-memory-elements/02-sram-architecture/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-06-memory-elements/02-sram-architecture/ The six-transistor SRAM cell, how it is read and written through a pair of bitlines, and how millions of them are organised into an array with decoders and sense amplifiers. https://circuit.quest/courses/digital-design-verilog/module-03/03-06-memory-elements/03-dram-and-memory-hierarchy/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-06-memory-elements/03-dram-and-memory-hierarchy/ The one-transistor DRAM cell, why reading it destroys the data, why it needs refreshing, the row buffer and the timing parameters, and where it all sits in the memory hierarchy. https://circuit.quest/courses/digital-design-verilog/module-03/03-06-memory-elements/04-rom-and-lookup-tables/ Sun, 01 Mar 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-03/03-06-memory-elements/04-rom-and-lookup-tables/ A ROM is a truth table in hardware. Mask ROM, PROM, EPROM, EEPROM and flash, the FPGA lookup table as a 16-by-1 ROM, and a look back over Module 3.