https://circuit.quest/courses/digital-design-verilog/module-02/ Recent content in Module 2: Combinational Circuit Design on Circuit Quest Hugo en-us Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-02/02-01-adder-circuits/01-the-addition-problem/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-02/02-01-adder-circuits/01-the-addition-problem/ Why addition in hardware is harder than addition on paper: the carry chain, what it costs in time, and the three ways designers get round it. https://circuit.quest/courses/digital-design-verilog/module-02/02-01-adder-circuits/02-half-adder-full-adder/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-02/02-01-adder-circuits/02-half-adder-full-adder/ The two smallest arithmetic circuits, derived from truth tables with Karnaugh maps and built from gates. https://circuit.quest/courses/digital-design-verilog/module-02/02-01-adder-circuits/03-ripple-carry-adder/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-02/02-01-adder-circuits/03-ripple-carry-adder/ Chain N full adders into an N-bit adder, trace it by hand, and work out why its delay grows with N. https://circuit.quest/courses/digital-design-verilog/module-02/02-01-adder-circuits/04-carry-lookahead-adder/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-02/02-01-adder-circuits/04-carry-lookahead-adder/ Generate and propagate signals let every carry be computed at once from the inputs, and that removes the serial chain of the ripple-carry adder. https://circuit.quest/courses/digital-design-verilog/module-02/02-01-adder-circuits/05-carry-select-adder/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-02/02-01-adder-circuits/05-carry-select-adder/ Compute each block’s result for both possible carry-ins, then select with a mux when the real carry arrives. Delay grows with the square root of the width. https://circuit.quest/courses/digital-design-verilog/module-02/02-01-adder-circuits/06-adder-tradeoffs/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-02/02-01-adder-circuits/06-adder-tradeoffs/ All the adder architectures compared on delay, area and power, the prefix adders that processors use, and why the answer is different on an FPGA. https://circuit.quest/courses/digital-design-verilog/module-02/02-02-subtractors-alu/01-subtraction-in-hardware/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-02/02-02-subtractors-alu/01-subtraction-in-hardware/ Subtraction needs no new hardware: invert one operand with XOR gates and set the carry-in to 1. Here is why that works, with worked examples and the overflow and borrow conditions. https://circuit.quest/courses/digital-design-verilog/module-02/02-02-subtractors-alu/02-adder-subtractor-unit/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-02/02-02-subtractors-alu/02-adder-subtractor-unit/ The complete 4-bit adder/subtractor with zero, negative, carry and overflow outputs, verified on four test cases and chained to 8 bits. https://circuit.quest/courses/digital-design-verilog/module-02/02-02-subtractors-alu/03-alu-design-philosophy/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-02/02-02-subtractors-alu/03-alu-design-philosophy/ The interface of an arithmetic logic unit, which operations belong in it, why every ALU computes everything at once and selects with a mux, and the 74181 that did it first. https://circuit.quest/courses/digital-design-verilog/module-02/02-02-subtractors-alu/04-building-the-alu/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-02/02-02-subtractors-alu/04-building-the-alu/ A complete 4-bit ALU with eight operations, built one unit at a time, traced end to end, with a gate count and timing. https://circuit.quest/courses/digital-design-verilog/module-02/02-02-subtractors-alu/05-alu-flags/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-02/02-02-subtractors-alu/05-alu-flags/ What the zero, negative, carry and overflow flags mean, how they are built, and how signed and unsigned comparisons are derived from them. https://circuit.quest/courses/digital-design-verilog/module-02/02-03-multipliers-shifters/01-binary-multiplication-by-hand/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-02/02-03-multipliers-shifters/01-binary-multiplication-by-hand/ Long multiplication in binary, partial products, and the one equation that every hardware multiplier implements. https://circuit.quest/courses/digital-design-verilog/module-02/02-03-multipliers-shifters/02-array-multiplier/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-02/02-03-multipliers-shifters/02-array-multiplier/ Long multiplication translated directly into hardware: an array of AND gates for the partial products and rows of adders to sum them. https://circuit.quest/courses/digital-design-verilog/module-02/02-03-multipliers-shifters/03-wallace-tree-multiplier/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-02/02-03-multipliers-shifters/03-wallace-tree-multiplier/ Carry-save adders reduce all the partial products at once, in a number of levels that grows with the logarithm of the width, and every fast multiplier is built this way. https://circuit.quest/courses/digital-design-verilog/module-02/02-03-multipliers-shifters/04-logical-arithmetic-shifts/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-02/02-03-multipliers-shifters/04-logical-arithmetic-shifts/ Shifts multiply and divide by powers of two for free. The one thing to get right is the difference between a logical and an arithmetic right shift. https://circuit.quest/courses/digital-design-verilog/module-02/02-03-multipliers-shifters/05-barrel-shifter/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-02/02-03-multipliers-shifters/05-barrel-shifter/ A circuit that shifts by any amount from 0 to N−1 in log₂N mux delays, using the binary digits of the shift amount to switch power-of-two stages in and out. https://circuit.quest/courses/digital-design-verilog/module-02/02-04-hazards/01-what-are-hazards/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-02/02-04-hazards/01-what-are-hazards/ A circuit with a correct Boolean expression can still put out a wrong value for a few picoseconds. Why that happens, the three kinds of hazard, and when a glitch matters. https://circuit.quest/courses/digital-design-verilog/module-02/02-04-hazards/02-static-hazards/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-02/02-04-hazards/02-static-hazards/ Finding static hazards on a Karnaugh map and removing them with a redundant term. https://circuit.quest/courses/digital-design-verilog/module-02/02-04-hazards/03-dynamic-hazards/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-02/02-04-hazards/03-dynamic-hazards/ An output that should change once but changes three or more times. Why it needs at least three levels of logic, how synthesis can create it, and how to remove it. https://circuit.quest/courses/digital-design-verilog/module-02/02-04-hazards/04-detecting-eliminating-hazards/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-02/02-04-hazards/04-detecting-eliminating-hazards/ A four-step method that finds and removes every static hazard in a two-level circuit, with a worked example, the POS version, and how don’t-cares interact. https://circuit.quest/courses/digital-design-verilog/module-02/02-04-hazards/05-hazards-in-practice/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-02/02-04-hazards/05-hazards-in-practice/ Four ways hazards cause real failures, the synchronous design principle and its limits, what the tools can and cannot see, and a look back over Module 2.