https://circuit.quest/courses/digital-design-verilog/module-01/ Recent content in Module 1: Foundations of Digital Logic on Circuit Quest Hugo en-us Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-01-number-systems/01-why-binary/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-01-number-systems/01-why-binary/ Why digital hardware works in ones and zeros: the noise margin argument, the alternatives that were tried, and the three people who connected logic to switches. https://circuit.quest/courses/digital-design-verilog/module-01/01-01-number-systems/02-number-bases/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-01-number-systems/02-number-bases/ Positional notation in any base, and the three bases a digital engineer uses every day. https://circuit.quest/courses/digital-design-verilog/module-01/01-01-number-systems/03-conversion-techniques/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-01-number-systems/03-conversion-techniques/ The conversion methods engineers actually use: repeated division, subtracting powers of two, and grouping bits in fours and threes. https://circuit.quest/courses/digital-design-verilog/module-01/01-01-number-systems/04-signed-numbers/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-01-number-systems/04-signed-numbers/ Sign-magnitude, one’s complement and two’s complement, and why the last one is what every CPU uses. https://circuit.quest/courses/digital-design-verilog/module-01/01-01-number-systems/05-binary-arithmetic/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-01-number-systems/05-binary-arithmetic/ How an adder works column by column, how subtraction reuses it, the two different kinds of overflow, and a first look at fixed-point fractions. https://circuit.quest/courses/digital-design-verilog/module-01/01-02-boolean-algebra/01-boolean-intro/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-02-boolean-algebra/01-boolean-intro/ The two-valued algebra that George Boole invented and Claude Shannon connected to switches, with truth tables and a worked example. https://circuit.quest/courses/digital-design-verilog/module-01/01-02-boolean-algebra/02-axioms-theorems/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-02-boolean-algebra/02-axioms-theorems/ Huntington’s postulates and the theorems that follow from them, each with a proof and with its meaning in terms of gates. https://circuit.quest/courses/digital-design-verilog/module-01/01-02-boolean-algebra/03-demorgan/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-02-boolean-algebra/03-demorgan/ The two identities you will use every day: how to complement an expression, how to read a schematic full of bubbles, and why CMOS is built from NAND and NOR. https://circuit.quest/courses/digital-design-verilog/module-01/01-02-boolean-algebra/04-canonical-forms/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-02-boolean-algebra/04-canonical-forms/ Minterms, maxterms, and the two standard ways of writing any truth table as an expression. https://circuit.quest/courses/digital-design-verilog/module-01/01-02-boolean-algebra/05-simplification/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-02-boolean-algebra/05-simplification/ Turning a canonical expression into something worth building: the tools, three worked examples, the redundant-term trick, and why we need Karnaugh maps. https://circuit.quest/courses/digital-design-verilog/module-01/01-03-logic-gates/01-gates-intro/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-03-logic-gates/01-gates-intro/ Before we catalogue the gates, let us be clear about what a gate physically is, and what propagation delay, fan-in and fan-out mean for the circuits you will build. https://circuit.quest/courses/digital-design-verilog/module-01/01-03-logic-gates/02-basic-gates/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-03-logic-gates/02-basic-gates/ AND, OR, NOT, NAND, NOR, XOR and XNOR: the symbol, truth table, Boolean expression, a typical use and the transistor cost of each. https://circuit.quest/courses/digital-design-verilog/module-01/01-03-logic-gates/03-compound-gates/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-03-logic-gates/03-compound-gates/ What a real standard cell library adds on top of the basic seven: multi-input gates, AOI and OAI compound cells, tri-state buffers, open-drain outputs and transmission gates. https://circuit.quest/courses/digital-design-verilog/module-01/01-03-logic-gates/04-universal-gates/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-03-logic-gates/04-universal-gates/ Any Boolean function can be built from NAND gates alone, or from NOR gates alone. Here is the proof, and why it matters for synthesis and for real silicon. https://circuit.quest/courses/digital-design-verilog/module-01/01-03-logic-gates/05-cmos-intuition/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-03-logic-gates/05-cmos-intuition/ The MOSFET as a switch, the CMOS inverter and NAND at transistor level, where the power goes, and what an RTL designer can do about it. https://circuit.quest/courses/digital-design-verilog/module-01/01-04-karnaugh-maps/01-why-kmaps/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-04-karnaugh-maps/01-why-kmaps/ A Karnaugh map is a truth table drawn so that terms which can be combined sit next to each other. This article explains the idea before we start using it. https://circuit.quest/courses/digital-design-verilog/module-01/01-04-karnaugh-maps/02-2var-3var-kmaps/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-04-karnaugh-maps/02-2var-3var-kmaps/ The grouping rules, prime implicants and essential prime implicants, worked on maps small enough to check by hand. https://circuit.quest/courses/digital-design-verilog/module-01/01-04-karnaugh-maps/03-4var-kmaps/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-04-karnaugh-maps/03-4var-kmaps/ Sixteen cells, the corner group, the full minimisation procedure, product-of-sums from the zeros, and functions with more than one minimal answer. https://circuit.quest/courses/digital-design-verilog/module-01/01-04-karnaugh-maps/04-dont-cares/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-04-karnaugh-maps/04-dont-cares/ Input combinations that never happen are free simplification on a Karnaugh map. Here is how to use them, with the seven-segment decoder as the example, and when to be careful. https://circuit.quest/courses/digital-design-verilog/module-01/01-04-karnaugh-maps/05-quine-mccluskey/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-04-karnaugh-maps/05-quine-mccluskey/ Karnaugh maps stop being useful at five or six variables. Quine-McCluskey does the same job as a procedure a computer can run, and it is the ancestor of what runs inside every synthesis tool. https://circuit.quest/courses/digital-design-verilog/module-01/01-05-combinational-blocks/01-multiplexers/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-05-combinational-blocks/01-multiplexers/ The multiplexer selects one of several inputs. It is the most common block in digital design, it can implement any Boolean function, and it is what an FPGA is made of. https://circuit.quest/courses/digital-design-verilog/module-01/01-05-combinational-blocks/02-demux-decoders/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-05-combinational-blocks/02-demux-decoders/ A decoder turns an n-bit code into one active output out of 2ⁿ. It is how memory chips get selected, and with an enable pin it is also a demultiplexer. https://circuit.quest/courses/digital-design-verilog/module-01/01-05-combinational-blocks/03-encoders-priority/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-05-combinational-blocks/03-encoders-priority/ An encoder is a decoder in reverse. A priority encoder is what you actually build, because in real systems more than one input is active at a time. https://circuit.quest/courses/digital-design-verilog/module-01/01-05-combinational-blocks/04-comparators/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-05-combinational-blocks/04-comparators/ Equality and magnitude comparison, the most-significant-bit-first structure, cascading, and the difference between signed and unsigned comparison that causes real bugs. https://circuit.quest/courses/digital-design-verilog/module-01/01-05-combinational-blocks/05-building-with-blocks/ Sat, 28 Feb 2026 00:00:00 +0000 https://circuit.quest/courses/digital-design-verilog/module-01/01-05-combinational-blocks/05-building-with-blocks/ How designers think in blocks rather than gates, a small ALU designed from a specification, buses and tri-state drivers, and a look back over Module 1.