Icarus Verilog is one of the most popular open-source Verilog simulators, widely used for learning digital design and verifying HDL code. Combined with GTKWave, a waveform viewer, it provides a complete simulation environment. In this tutorial, we’ll install both tools and create a simple multiplexer design to demonstrate the workflow.

SystemVerilog is a powerful hardware description and verification language used in modern digital design. In this tutorial, we’ll walk through setting up a complete simulation environment using Verilator (a fast, open-source simulator) and Surfer (a modern waveform viewer), then create and simulate a simple multiplexer design.

OpenLane is an automated RTL to GDSII flow based on several open-source tools, enabling complete physical chip design. It uses OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, KLayout along with other scripts and flows for to take a design from RTL to GDSII. This guide walks through setting up OpenLane using Ubuntu 25.04 and Docker.